soc/intel: Move pch_misc_init() to common code
List of changes:
1. Move pch_misc_init() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index e220678..b21c117 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -90,18 +90,6 @@
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-static void pch_misc_init(void)
-{
- uint8_t reg8;
-
- /* Setup NMI on errors, disable SERR */
- reg8 = (inb(0x61)) & 0xf0;
- outb((reg8 | (1 << 2)), 0x61);
-
- /* Disable NMI sources */
- outb((1 << 7), 0x70);
-};
-
void lpc_soc_init(struct device *dev)
{
const config_t *config = dev->chip_info;
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 52b0ff8..b04df76 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -109,5 +109,11 @@
void pch_enable_ioapic(void);
/* Retrieve and setup PCH LPC interrupt routing. */
void pch_pirq_init(void);
+/*
+ * LPC MISC programming
+ * 1. Setup NMI on errors, disable SERR
+ * 2. Disable NMI sources
+ */
+void pch_misc_init(void);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index d189a5e..67dd661 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -386,3 +386,21 @@
pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line);
}
}
+
+#define PPI_PORT_B 0x61
+#define SERR_DIS (1 << 2)
+#define CMOS_NMI 0x70
+#define NMI_DIS (1 << 7)
+
+/* LPC MISC programming */
+void pch_misc_init(void)
+{
+ uint8_t reg8;
+
+ /* Setup NMI on errors, disable SERR */
+ reg8 = (inb(PPI_PORT_B)) & 0xf0;
+ outb((reg8 | SERR_DIS), PPI_PORT_B);
+
+ /* Disable NMI sources */
+ outb(NMI_DIS, CMOS_NMI);
+}
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
index 6e6f887..a531fcc 100644
--- a/src/soc/intel/elkhartlake/espi.c
+++ b/src/soc/intel/elkhartlake/espi.c
@@ -64,18 +64,6 @@
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-static void pch_misc_init(void)
-{
- uint8_t reg8;
-
- /* Setup NMI on errors, disable SERR */
- reg8 = (inb(NMI_STS_CNT) & 0xf0);
- outb((reg8 | (1 << 2)), NMI_STS_CNT);
-
- /* Disable NMI sources */
- outb((1 << 7), NMI_EN);
-};
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
diff --git a/src/soc/intel/elkhartlake/include/soc/espi.h b/src/soc/intel/elkhartlake/include/soc/espi.h
index 6c26158..65ee732 100644
--- a/src/soc/intel/elkhartlake/include/soc/espi.h
+++ b/src/soc/intel/elkhartlake/include/soc/espi.h
@@ -22,8 +22,6 @@
#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */
#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */
#define LGMR 0x98 /* ESPI Generic Memory Range */
-#define NMI_EN 0x70
-#define NMI_STS_CNT 0x61
#define PCCTL 0xE0 /* PCI Clock Control */
#define CLKRUN_EN (1 << 0)
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c
index 388d9fa..7f9ff2f 100644
--- a/src/soc/intel/icelake/espi.c
+++ b/src/soc/intel/icelake/espi.c
@@ -83,18 +83,6 @@
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-static void pch_misc_init(void)
-{
- uint8_t reg8;
-
- /* Setup NMI on errors, disable SERR */
- reg8 = (inb(0x61)) & 0xf0;
- outb((reg8 | (1 << 2)), 0x61);
-
- /* Disable NMI sources */
- outb((1 << 7), 0x70);
-};
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
index ef1ed95..0977857 100644
--- a/src/soc/intel/jasperlake/espi.c
+++ b/src/soc/intel/jasperlake/espi.c
@@ -65,18 +65,6 @@
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-static void pch_misc_init(void)
-{
- uint8_t reg8;
-
- /* Setup NMI on errors, disable SERR */
- reg8 = (inb(0x61)) & 0xf0;
- outb((reg8 | (1 << 2)), 0x61);
-
- /* Disable NMI sources */
- outb((1 << 7), 0x70);
-};
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 0eaeb9f..f9c6639 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -49,10 +49,6 @@
}
static const struct reg_script pch_misc_init_script[] = {
- /* Setup NMI on errors, disable SERR */
- REG_IO_RMW8(0x61, ~0xf0, (1 << 2)),
- /* Disable NMI sources */
- REG_IO_OR8(0x70, (1 << 7)),
/* Enable BIOS updates outside of SMM */
REG_PCI_RMW8(0xdc, ~(1 << 5), 0),
REG_SCRIPT_END
@@ -64,6 +60,7 @@
/* Legacy initialization */
isa_dma_init();
+ pch_misc_init();
reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
/* Enable CLKRUN_EN for power gating LPC */
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index 668e95f..acd3b12 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -71,18 +71,6 @@
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-static void pch_misc_init(void)
-{
- uint8_t reg8;
-
- /* Setup NMI on errors, disable SERR */
- reg8 = (inb(0x61)) & 0xf0;
- outb((reg8 | (1 << 2)), 0x61);
-
- /* Disable NMI sources */
- outb((1 << 7), 0x70);
-};
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */