commit 8950cfb66f8f1fd4b047fbef2347134be0aeacec
author Kyösti Mälkki <kyosti.malkki@gmail.com> Sat Jul 13 22:16:25 2019 +0300
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Thu Jul 18 15:25:35 2019 +0000
tree 57943bfb4f8d74c2d1a4bfbd2a9813ac27e510dd
parent 4af4e7f06eddad71f86eda3e401967e79d3a9ddb

soc/intel: Use config_of()

Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian

src/soc/intel/broadwell/pcie.c

diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index dff4f81..bdaced2 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -135,10 +135,8 @@
 		root_port_config_update_gbe_port();
 
 		pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
-		if (dev->chip_info != NULL) {
-			config_t *config = dev->chip_info;
-			rpc.coalesce = config->pcie_port_coalesce;
-		}
+		config_t *config = config_of(dev);
+		rpc.coalesce = config->pcie_port_coalesce;
 	}
 
 	rp = root_port_number(dev);
@@ -449,7 +447,7 @@
 
 static void pch_pcie_early(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
 	int do_aspm = 0;
 	int rp = root_port_number(dev);
 
@@ -481,7 +479,7 @@
 	}
 
 	/* Allow ASPM to be forced on in devicetree */
-	if (config && (config->pcie_port_force_aspm & (1 << (rp - 1))))
+	if ((config->pcie_port_force_aspm & (1 << (rp - 1))))
 		do_aspm = 1;
 
 	printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",