soc/intel: Use config_of()
Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 7658515..c4023cc 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -31,7 +31,7 @@
static void adsp_init(struct device *dev)
{
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
struct resource *bar0, *bar1;
u32 tmp32;
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 9107b23..dab2d15 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -298,7 +298,7 @@
static void igd_setup_panel(struct device *dev)
{
- config_t *conf = dev->chip_info;
+ config_t *conf = config_of(dev);
u32 reg32;
/* Setup Digital Port Hotplug */
@@ -349,7 +349,7 @@
static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
struct device *const dev)
{
- const config_t *const conf = dev->chip_info;
+ const config_t *const conf = config_of(dev);
int cdclk = conf->cdclk;
/* Check for ULX GT1 or GT2 */
@@ -383,7 +383,7 @@
struct device *const dev)
{
static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
- const config_t *const conf = dev->chip_info;
+ const config_t *const conf = config_of(dev);
int cdclk = conf->cdclk;
/* Check for ULX */
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index df1d857..9be4aeb 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -104,7 +104,7 @@
static void pch_pirq_init(struct device *dev)
{
struct device *irq_dev;
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
@@ -151,7 +151,7 @@
u16 reg16;
const char *state;
/* Get the chip configuration */
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* Which state do we want to goto after g3 (power restored)?
@@ -318,7 +318,7 @@
static void pch_init_deep_sx(struct device *dev)
{
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
if (config->deep_sx_enable_ac) {
RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
@@ -550,7 +550,7 @@
static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
/* Add the default claimed IO range for the LPC device. */
res = new_resource(dev, 0);
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index dd5e5b8..6be1748 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -971,7 +971,7 @@
/* Check whether ME is present and do basic init */
static void intel_me_init(struct device *dev)
{
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
me_bios_path path = intel_me_path(dev);
me_bios_payload mbp_data;
int mbp_ret;
@@ -1004,7 +1004,7 @@
intel_me_print_mbp(&mbp_data);
/* Set clock enables according to devicetree */
- if (config && config->icc_clock_disable)
+ if (config->icc_clock_disable)
me_icc_set_clock_enables(config->icc_clock_disable);
/* Make sure ME is in a mode that expects EOP */
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index dff4f81..bdaced2 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -135,10 +135,8 @@
root_port_config_update_gbe_port();
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
- if (dev->chip_info != NULL) {
- config_t *config = dev->chip_info;
- rpc.coalesce = config->pcie_port_coalesce;
- }
+ config_t *config = config_of(dev);
+ rpc.coalesce = config->pcie_port_coalesce;
}
rp = root_port_number(dev);
@@ -449,7 +447,7 @@
static void pch_pcie_early(struct device *dev)
{
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
int do_aspm = 0;
int rp = root_port_number(dev);
@@ -481,7 +479,7 @@
}
/* Allow ASPM to be forced on in devicetree */
- if (config && (config->pcie_port_force_aspm & (1 << (rp - 1))))
+ if ((config->pcie_port_force_aspm & (1 << (rp - 1))))
do_aspm = 1;
printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index ea2726b..0bd4ccd 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -76,13 +76,9 @@
static void pch_enable_lpc(void)
{
/* Lookup device tree in romstage */
- const struct device *dev;
const config_t *config;
- dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
- if (!dev || !dev->chip_info)
- return;
- config = dev->chip_info;
+ config = config_of_path(PCH_DEVFN_LPC);
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index cb08ae7..e47a78d 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -41,7 +41,7 @@
static void sata_init(struct device *dev)
{
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
u32 reg32;
u8 *abar;
u16 reg16;
@@ -271,7 +271,7 @@
static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
u16 map = 0x0060;
map |= (config->sata_port_map ^ 0xf) << 8;
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 12e458c..161c875 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -170,7 +170,7 @@
static void serialio_init(struct device *dev)
{
- config_t *config = dev->chip_info;
+ config_t *config = config_of(dev);
struct resource *bar0, *bar1;
int sio_index = -1;
u32 reg32;