src/soc/intel/apollolake/Kconfig

config SOC_INTEL_APOLLOLAKE
	bool
	help
	  Intel Apollolake support

if SOC_INTEL_APOLLOLAKE

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_RAMSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_VERSTAGE_X86_32
	# CPU specific options
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select IOAPIC
	select SMP
	select SSE2
	select SUPPORT_CPU_UCODE_IN_CBFS
	# Misc options
	select C_ENVIRONMENT_BOOTBLOCK
	select COLLECT_TIMESTAMPS
	select COMMON_FADT
	select HAVE_INTEL_FIRMWARE
	select MMCONF_SUPPORT
	select MMCONF_SUPPORT_DEFAULT
	select NO_FIXED_XIP_ROM_SIZE
	select NO_STAGE_CACHE
	select NO_XIP_EARLY_STAGES
	select PARALLEL_MP
	select PCIEXP_ASPM
	select PCIEXP_COMMON_CLOCK
	select PCIEXP_CLK_PM
	select PCIEXP_L1_SUB_STATE
	select POSTCAR_STAGE
	select REG_SCRIPT
	select RELOCATABLE_RAMSTAGE	# Build fails if this is not selected
	select SOC_INTEL_COMMON
	select SPI_FLASH
	select UDELAY_TSC
	select TSC_CONSTANT_RATE
	select TSC_MONOTONIC_TIMER
	select HAVE_MONOTONIC_TIMER
	select PLATFORM_USES_FSP2_0
	select HAVE_HARD_RESET
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_GFX_OPREGION
	select ADD_VBT_DATA_FILE

config TPM_ON_FAST_SPI
	bool
	default n
	select LPC_TPM
	help
	 TPM part is conntected on Fast SPI interface, but the LPC MMIO
	 TPM transactions are decoded and serialized over the SPI interface.

config SOC_INTEL_COMMON_RESET
	bool
	default y

config MMCONF_BASE_ADDRESS
	hex "PCI MMIO Base Address"
	default 0xe0000000

config IOSF_BASE_ADDRESS
	hex "MMIO Base Address of sideband bus"
	default 0xd0000000

config DCACHE_RAM_BASE
	hex "Base address of cache-as-RAM"
	default 0xfef00000

config DCACHE_RAM_SIZE
	hex "Length in bytes of cache-as-RAM"
	default 0x80000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x4000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages.

config CPU_ADDR_BITS
	int
	default 36

config CONSOLE_UART_BASE_ADDRESS
	depends on CONSOLE_SERIAL
	hex "MMIO base address for UART"
	default 0xde000000

config SOC_UART_DEBUG
	bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
	default n
	select CONSOLE_SERIAL
	select BOOTBLOCK_CONSOLE
	select DRIVERS_UART
	select DRIVERS_UART_8250MEM_32
	select NO_UART_ON_SUPERIO

# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0x8000

# This SoC does not map SPI flash like many previous SoC. Therefore we provide
# a custom media driver that facilitates mapping
config X86_TOP4G_BOOTMEDIA_MAP
	bool
	default n

config ROMSTAGE_ADDR
	hex
	default 0xfef2e000
	help
	  The base address (in CAR) where romstage should be linked

config CACHE_MRC_SETTINGS
	bool
	default y

endif