| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2017 Advanced Micro Devices, Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config SOC_AMD_STONEYRIDGE_FP4 |
| bool |
| help |
| AMD Stoney Ridge FP4 support |
| |
| config SOC_AMD_STONEYRIDGE_FT4 |
| bool |
| help |
| AMD Stoney Ridge FT4 support |
| |
| if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_VERSTAGE_X86_32 |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select X86_AMD_FIXED_MTRRS |
| select ACPI_AMD_HARDWARE_SLEEP_VALUES |
| select COLLECT_TIMESTAMPS_NO_TSC |
| select DRIVERS_I2C_DESIGNWARE |
| select GENERIC_GPIO_LIB |
| select GENERIC_UDELAY |
| select IOAPIC |
| select HAVE_USBDEBUG_OPTIONS |
| select HAVE_HARD_RESET |
| select HAVE_MONOTONIC_TIMER |
| select SPI_FLASH if HAVE_ACPI_RESUME |
| select TSC_SYNC_LFENCE |
| select COLLECT_TIMESTAMPS |
| select SOC_AMD_PI |
| select SOC_AMD_COMMON |
| select SOC_AMD_COMMON_BLOCK |
| select SOC_AMD_COMMON_BLOCK_PCI |
| select SOC_AMD_COMMON_BLOCK_PI |
| select SOC_AMD_COMMON_BLOCK_PSP |
| select SOC_AMD_COMMON_BLOCK_CAR |
| select SOC_AMD_COMMON_BLOCK_S3 if HAVE_ACPI_RESUME |
| select C_ENVIRONMENT_BOOTBLOCK |
| select BOOTBLOCK_CONSOLE |
| select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
| select PARALLEL_MP |
| select PARALLEL_MP_AP_WORK |
| select HAVE_SMI_HANDLER |
| select SMM_TSEG |
| select POSTCAR_STAGE |
| select POSTCAR_CONSOLE |
| select SSE |
| select SSE2 |
| select RTC |
| |
| config VBOOT |
| select VBOOT_SEPARATE_VERSTAGE |
| select VBOOT_STARTS_IN_BOOTBLOCK |
| select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| select VBOOT_VBNV_CMOS |
| select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| |
| config UDELAY_LAPIC_FIXED_FSB |
| int |
| default 200 |
| |
| # TODO: Sync these with definitions in PI vendorcode. |
| # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0x30000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x10000 |
| |
| config DCACHE_BSP_STACK_SIZE |
| depends on C_ENVIRONMENT_BOOTBLOCK |
| hex |
| default 0x4000 |
| help |
| The amount of anticipated stack usage in CAR by bootblock and |
| other stages. |
| |
| config PRERAM_CBMEM_CONSOLE_SIZE |
| hex |
| default 0x1600 |
| help |
| Increase this value if preram cbmem console is getting truncated |
| |
| config CPU_ADDR_BITS |
| int |
| default 48 |
| |
| config BOTTOMIO_POSITION |
| hex "Bottom of 32-bit IO space" |
| default 0xD0000000 |
| help |
| If PCI peripherals with big BARs are connected to the system |
| the bottom of the IO must be decreased to allocate such |
| devices. |
| |
| Declare the beginning of the 128MB-aligned MMIO region. This |
| option is useful when PCI peripherals requesting large address |
| ranges are present. |
| |
| config MMCONF_BASE_ADDRESS |
| hex |
| default 0xF8000000 |
| |
| config MMCONF_BUS_NUMBER |
| int |
| default 64 |
| |
| config VGA_BIOS_ID |
| string |
| default "1002,98e4" |
| help |
| The default VGA BIOS PCI vendor/device ID should be set to the |
| result of the map_oprom_vendev() function in northbridge.c. |
| |
| config VGA_BIOS_FILE |
| string |
| default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" |
| |
| config S3_VGA_ROM_RUN |
| bool |
| default n |
| |
| config HEAP_SIZE |
| hex |
| default 0xc0000 |
| |
| config SOUTHBRIDGE_AMD_STONEYRIDGE_SKIP_ISA_DMA_INIT |
| bool |
| default n |
| |
| config EHCI_BAR |
| hex |
| default 0xfef00000 |
| |
| config STONEYRIDGE_XHCI_ENABLE |
| bool "Enable Stoney Ridge XHCI Controller" |
| default y |
| help |
| The XHCI controller must be enabled and the XHCI firmware |
| must be added in order to have USB 3.0 support configured |
| by coreboot. The OS will be responsible for enabling the XHCI |
| controller if the the XHCI firmware is available but the |
| XHCI controller is not enabled by coreboot. |
| |
| config STONEYRIDGE_XHCI_FWM |
| bool "Add xhci firmware" |
| default y |
| help |
| Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 |
| |
| config STONEYRIDGE_IMC_FWM |
| bool "Add IMC firmware" |
| default n |
| help |
| Add Stoney Ridge IMC Firmware to support the onboard fan control |
| |
| config STONEYRIDGE_GEC_FWM |
| bool |
| default n |
| help |
| Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. |
| Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
| |
| config STONEYRIDGE_XHCI_FWM_FILE |
| string "XHCI firmware path and filename" |
| default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" |
| depends on STONEYRIDGE_XHCI_FWM |
| |
| config STONEYRIDGE_IMC_FWM_FILE |
| string "IMC firmware path and filename" |
| default "3rdparty/blobs/soc/amd/stoneyridge/imc.bin" |
| depends on STONEYRIDGE_IMC_FWM |
| |
| config STONEYRIDGE_GEC_FWM_FILE |
| string "GEC firmware path and filename" |
| depends on STONEYRIDGE_GEC_FWM |
| |
| config AMD_PUBKEY_FILE |
| string "AMD public Key" |
| default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" |
| |
| config STONEYRIDGE_SATA_MODE |
| int "SATA Mode" |
| default 0 |
| range 0 6 |
| help |
| Select the mode in which SATA should be driven. |
| The default is NATIVE. |
| 0: NATIVE mode does not require a ROM. |
| 2: AHCI may work with or without AHCI ROM. It depends on the payload support. |
| For example, seabios does not require the AHCI ROM. |
| 3: LEGACY IDE |
| 4: IDE to AHCI |
| 5: AHCI7804: ROM Required, and AMD driver required in the OS. |
| 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. |
| |
| comment "NATIVE" |
| depends on STONEYRIDGE_SATA_MODE = 0 |
| |
| comment "AHCI" |
| depends on STONEYRIDGE_SATA_MODE = 2 |
| |
| comment "LEGACY IDE" |
| depends on STONEYRIDGE_SATA_MODE = 3 |
| |
| comment "IDE to AHCI" |
| depends on STONEYRIDGE_SATA_MODE = 4 |
| |
| comment "AHCI7804" |
| depends on STONEYRIDGE_SATA_MODE = 5 |
| |
| comment "IDE to AHCI7804" |
| depends on STONEYRIDGE_SATA_MODE = 6 |
| |
| if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 |
| |
| config AHCI_ROM_ID |
| string "AHCI device PCI IDs" |
| default "1022,7801" if STONEYRIDGE_SATA_MODE = 2 |
| default "1022,7804" if STONEYRIDGE_SATA_MODE = 5 |
| |
| endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 |
| |
| config STONEYRIDGE_LEGACY_FREE |
| bool "System is legacy free" |
| help |
| Select y if there is no keyboard controller in the system. |
| This sets variables in AGESA and ACPI. |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default n |
| help |
| Set this option to y for serial IRQ in continuous mode. |
| Otherwise it is in quiet mode. |
| |
| config STONEYRIDGE_ACPI_IO_BASE |
| hex |
| default 0x400 |
| help |
| Base address for the ACPI registers. |
| This value must match the hardcoded value of AGESA. |
| |
| config STONEYRIDGE_UART |
| bool "UART controller on Stoney Ridge" |
| default n |
| select DRIVERS_UART_8250MEM |
| select DRIVERS_UART_8250MEM_32 |
| select NO_UART_ON_SUPERIO |
| select UART_OVERRIDE_REFCLK |
| help |
| There are two UART controllers in Stoney Ridge. |
| The UART registers are memory-mapped. UART |
| controller 0 registers range from FEDC_6000h |
| to FEDC_6FFFh. UART controller 1 registers |
| range from FEDC_8000h to FEDC_8FFFh. |
| |
| config CONSOLE_UART_BASE_ADDRESS |
| depends on CONSOLE_SERIAL |
| hex |
| default 0xfedc6000 |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
| default 0x0 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x150000 |
| |
| config SMM_MODULE_STACK_SIZE |
| hex |
| default 0x800 |
| |
| config ACPI_CPU_STRING |
| string |
| default "\\_PR.P%03d" |
| |
| config USE_PSPSCUREOS |
| bool "Include PSP SecureOS blobs in AMD firmware" |
| default y |
| help |
| Include the PspSecureOs, PspTrustlet and TrustletKey binaries |
| in the amdfw section. |
| |
| If unsure, answer 'y' |
| |
| config SOC_AMD_SMU_FANLESS |
| bool |
| depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| default n if SOC_AMD_SMU_NOTFANLESS |
| default y |
| |
| config SOC_AMD_SMU_FANNED |
| bool |
| depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| default n |
| select SOC_AMD_SMU_NOTFANLESS |
| |
| config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use |
| bool |
| depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| |
| config AMDFW_OUTSIDE_CBFS |
| bool "The AMD firmware is outside CBFS" |
| default n |
| help |
| The AMDFW (PSP) is typically locatable in cbfs. Select this |
| option to manually attach the generated amdfw.rom outside of |
| cbfs. The location is selected by the FWM position. |
| |
| config AMD_FWM_POSITION_INDEX |
| int "Firmware Directory Table location (0 to 5)" |
| range 0 5 |
| default 0 if BOARD_ROMSIZE_KB_512 |
| default 1 if BOARD_ROMSIZE_KB_1024 |
| default 2 if BOARD_ROMSIZE_KB_2048 |
| default 3 if BOARD_ROMSIZE_KB_4096 |
| default 4 if BOARD_ROMSIZE_KB_8192 |
| default 5 if BOARD_ROMSIZE_KB_16384 |
| help |
| Typically this is calculated by the ROM size, but there may |
| be situations where you want to put the firmware directory |
| table in a different location. |
| 0: 512 KB - 0xFFFA0000 |
| 1: 1 MB - 0xFFF20000 |
| 2: 2 MB - 0xFFE20000 |
| 3: 4 MB - 0xFFC20000 |
| 4: 8 MB - 0xFF820000 |
| 5: 16 MB - 0xFF020000 |
| |
| comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 0 |
| comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 1 |
| comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 2 |
| comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 3 |
| comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 4 |
| comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 5 |
| |
| config DIMM_SPD_SIZE |
| int |
| default 512 # DDR4 |
| |
| config RO_REGION_ONLY |
| string |
| depends on CHROMEOS |
| default "apu/amdfw" |
| |
| config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| int |
| default 133 |
| |
| config MAINBOARD_POWER_RESTORE |
| def_bool n |
| help |
| This option determines what state to go to once power is restored |
| after having been lost in S0. Select this option to automatically |
| return to S0. Otherwise the system will remain in S5 once power |
| is restored. |
| |
| config VENDORCODE_FULL_SUPPORT |
| def_bool n |
| help |
| This option determines if all files under |
| vendorcode/amd/pi/00670F00/ will be compiled or only |
| selected procedures of source files (minimum required). |
| |
| endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 |