| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2019 Intel Corporation. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <console/console.h> |
| #include <device/device.h> |
| #include <device/pci.h> |
| #include <fsp/api.h> |
| #include <fsp/util.h> |
| #include <intelblocks/lpss.h> |
| #include <intelblocks/xdci.h> |
| #include <soc/gpio_soc_defs.h> |
| #include <soc/intel/common/vbt.h> |
| #include <soc/pci_devs.h> |
| #include <soc/ramstage.h> |
| #include <soc/soc_chip.h> |
| #include <string.h> |
| |
| static void parse_devicetree(FSP_S_CONFIG *params) |
| { |
| const struct soc_intel_tigerlake_config *config; |
| config = config_of_soc(); |
| |
| for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| |
| for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| } |
| |
| for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| } |
| |
| static const pci_devfn_t serial_io_dev[] = { |
| PCH_DEVFN_I2C0, |
| PCH_DEVFN_I2C1, |
| PCH_DEVFN_I2C2, |
| PCH_DEVFN_I2C3, |
| PCH_DEVFN_I2C4, |
| PCH_DEVFN_I2C5, |
| PCH_DEVFN_GSPI0, |
| PCH_DEVFN_GSPI1, |
| PCH_DEVFN_GSPI2, |
| PCH_DEVFN_GSPI3, |
| PCH_DEVFN_UART0, |
| PCH_DEVFN_UART1, |
| PCH_DEVFN_UART2 |
| }; |
| |
| /* UPD parameters to be initialized before SiliconInit */ |
| void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| { |
| int i; |
| FSP_S_CONFIG *params = &supd->FspsConfig; |
| |
| struct device *dev; |
| struct soc_intel_tigerlake_config *config; |
| config = config_of_soc(); |
| |
| /* Parse device tree and enable/disable Serial I/O devices */ |
| parse_devicetree(params); |
| |
| /* Load VBT before devicetree-specific config. */ |
| params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| |
| params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; |
| |
| dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) |
| params->PeiGraphicsPeimInit = 1; |
| else |
| params->PeiGraphicsPeimInit = 0; |
| |
| for (i = 0; i < 8; i++) |
| params->IomTypeCPortPadCfg[i] = 0x09000000; |
| |
| /* USB */ |
| for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| } |
| |
| for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| if (config->usb3_ports[i].tx_de_emp) { |
| params->Usb3HsioTxDeEmphEnable[i] = 1; |
| params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| } |
| if (config->usb3_ports[i].tx_downscale_amp) { |
| params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| params->Usb3HsioTxDownscaleAmp[i] = |
| config->usb3_ports[i].tx_downscale_amp; |
| } |
| } |
| |
| /* Enable xDCI controller if enabled in devicetree and allowed */ |
| dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); |
| if (!xdci_can_enable()) |
| dev->enabled = 0; |
| params->XdciEnable = dev->enabled; |
| |
| /* PCH UART selection for FSP Debug */ |
| params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| |
| /* SATA */ |
| dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); |
| if (!dev) |
| params->SataEnable = 0; |
| else { |
| params->SataEnable = dev->enabled; |
| params->SataMode = config->SataMode; |
| params->SataSalpSupport = config->SataSalpSupport; |
| memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| sizeof(params->SataPortsEnable)); |
| memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| sizeof(params->SataPortsDevSlp)); |
| } |
| |
| mainboard_silicon_init_params(params); |
| } |
| |
| /* Mainboard GPIO Configuration */ |
| __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| { |
| printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| } |
| |
| /* Return list of SOC LPSS controllers */ |
| const pci_devfn_t *soc_lpss_controllers_list(size_t *size) |
| { |
| *size = ARRAY_SIZE(serial_io_dev); |
| return serial_io_dev; |
| } |