commit 7d8c832d1fa9fca354f93571bf0c4b8905de86d8
author Felix Held <felix-coreboot@felixheld.de> Sat Mar 25 04:59:18 2023 +0100
committer Felix Held <felix-coreboot@felixheld.de> Wed Mar 29 16:30:32 2023 +0000
tree f2a552dd382432b1d7ec3354e043e608d2f03ff8
parent 23cae54e5dc4d546412db7299b8ff52f1bb0135c

soc/amd/stoneyridge/cpu: implement get_pstate_latency

Both the algorithm and the registers involved are described in the
public version of BKDG #55072 Rev 3.09 in chapter 2.5.2.1.7.3.2 _PSS
(Performance Supported States).

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b2c177d9d80c5c205340f3f428186d6b8eb7e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/soc/amd/stoneyridge/Kconfig

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 0d790a3..6f5c6e0 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -39,6 +39,7 @@
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_SMM
+	select SOC_AMD_COMMON_BLOCK_SMN
 	select SOC_AMD_COMMON_BLOCK_SPI
 	select SOC_AMD_COMMON_BLOCK_SVI2
 	select SOC_AMD_COMMON_BLOCK_UART

src/soc/amd/stoneyridge/cpu.c

diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 2f4c0d0..c5c2f68 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -4,6 +4,7 @@
 #include <amdblocks/iomap.h>
 #include <amdblocks/mca.h>
 #include <amdblocks/reset.h>
+#include <amdblocks/smn.h>
 #include <cpu/amd/msr.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
@@ -14,6 +15,7 @@
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
+#include <soc/msr.h>
 #include <console/console.h>
 #include <types.h>
 
@@ -75,3 +77,50 @@
 {
 	return (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7;
 }
+
+static bool all_pstates_have_same_frequency_id(void)
+{
+	union pstate_msr pstate_reg;
+	size_t i;
+	bool first = true;
+	uint32_t frequency_id;
+
+	for (i = 0; i < 7; i++) {
+		pstate_reg.raw = rdmsr(PSTATE_MSR(i)).raw;
+
+		if (!pstate_reg.pstate_en)
+			continue;
+
+		if (first) {
+			frequency_id = pstate_reg.cpu_fid_0_5;
+			first = false;
+		} else if (frequency_id != pstate_reg.cpu_fid_0_5) {
+			return false;
+		}
+	}
+
+	return true;
+}
+
+#define CLK_PLL_LOCK_TIMER		0xD82220B8
+#define CLK_GATER_SEQUENCE_REGISTER	0xD8222114
+
+uint32_t get_pstate_latency(void)
+{
+	uint32_t latency = 0;
+	uint32_t smn_data;
+	uint32_t gaters_on_time, gaters_off_time;
+
+	smn_data = smn_read32(CLK_GATER_SEQUENCE_REGISTER);
+	gaters_on_time = (smn_data & 0xff) * 10;
+	gaters_off_time = (smn_data >> 8 & 0xff) * 10;
+	latency += DIV_ROUND_UP(15 * gaters_on_time, 1000);
+	latency += DIV_ROUND_UP(15 * gaters_off_time, 1000);
+
+	if (!all_pstates_have_same_frequency_id()) {
+		smn_data = smn_read32(CLK_PLL_LOCK_TIMER);
+		latency += DIV_ROUND_UP(smn_data & 0x1fff, 100);
+	}
+
+	return latency;
+}