Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
7cba1c486beb9287dc563784904d2a8e0235340a
/
.
/
src
/
soc
/
intel
/
apollolake
/
include
/
soc
/
ramstage.h
blob: fa096a476a1dc68cfa22d2f4833b853581ebc4be [
file
] [
log
] [
blame
]
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef
_SOC_APOLLOLAKE_RAMSTAGE_H_
#define
_SOC_APOLLOLAKE_RAMSTAGE_H_
#include
<fsp/api.h>
void
mainboard_silicon_init_params
(
FSP_S_CONFIG
*
silconfig
);
#endif
/* _SOC_APOLLOLAKE_RAMSTAGE_H_ */