Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
7b73e85283bea7f456ab2f86ed1d1099eb88bc2f
/
.
/
src
/
cpu
/
x86
/
Kconfig.debug_cpu
blob: 8e0c3e423386ef6afe556a1cd670320a28cda757 [
file
] [
log
] [
blame
]
if
ARCH_X86
config HAVE_DEBUG_CAR
bool
config DEBUG_CAR
bool
"Output verbose Cache-as-RAM debug messages"
depends on HAVE_DEBUG_CAR
config DISPLAY_MTRRS
bool
"Display intermediate MTRR settings"
endif
# ARCH_X86