commit 77334d49842f82497dbbcbd0da43bb134016198e
author Subrata Banik <subratabanik@google.com> Mon Apr 18 11:30:38 2022 +0530
committer Felix Held <felix-coreboot@felixheld.de> Thu Apr 21 13:07:58 2022 +0000
tree 23a976e225a2f3ca69714a1f2d6a642837f01e32
parent bca2f02ab7763f788db04c52673e7ba9d1a4b127

soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP)

This patch implements two APIs to perform LPC/eSPI write protect enable/
disable operation using PCI configuration space register 0xDC
(BIOS Controller).

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8ce831218025a1d682ea2ad6be76901b0345b362
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/common/block/lpc/lpc_lib.c

diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 654dcea..cdaeae1 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -195,6 +195,31 @@
 	lpc_set_bios_control_reg(LPC_BC_EISS);
 }
 
+static void lpc_configure_write_protect(bool status)
+{
+	const pci_devfn_t dev = PCH_DEV_LPC;
+	uint8_t bios_cntl;
+
+	bios_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);
+	if (status)
+		bios_cntl &= ~LPC_BC_WPD;
+	else
+		bios_cntl |= LPC_BC_WPD;
+	pci_write_config8(dev, LPC_BIOS_CNTL, bios_cntl);
+}
+
+/* Enable LPC Write Protect. */
+void lpc_enable_wp(void)
+{
+	lpc_configure_write_protect(true);
+}
+
+/* Disable LPC Write Protect. */
+void lpc_disable_wp(void)
+{
+	lpc_configure_write_protect(false);
+}
+
 /*
 * Set LPC Serial IRQ mode.
 */