| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2004 Eric Biederman |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; version 2 of |
| * the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef I82801DX_CHIP_H |
| #define I82801DX_CHIP_H |
| |
| struct southbridge_intel_i82801dx_config { |
| int enable_usb; |
| int enable_native_ide; |
| /** |
| * Interrupt Routing configuration |
| * If bit7 is 1, the interrupt is disabled. |
| */ |
| uint8_t pirqa_routing; |
| uint8_t pirqb_routing; |
| uint8_t pirqc_routing; |
| uint8_t pirqd_routing; |
| uint8_t pirqe_routing; |
| uint8_t pirqf_routing; |
| uint8_t pirqg_routing; |
| uint8_t pirqh_routing; |
| |
| uint8_t ide0_enable; |
| uint8_t ide1_enable; |
| }; |
| |
| #endif /* I82801DBM_CHIP_H */ |