| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <console/console.h> |
| #include <device/device.h> |
| #include <device/pci.h> |
| #include <device/pci_ids.h> |
| #include <device/pci_ops.h> |
| #include <device/smbus.h> |
| #include <pc80/mc146818rtc.h> |
| #include <arch/io.h> |
| #include <cpu/x86/lapic.h> |
| #include <arch/ioapic.h> |
| #include <stdlib.h> |
| #include "hudson.h" |
| #include "smbus.c" |
| |
| #define NMI_OFF 0 |
| |
| #define MAINBOARD_POWER_OFF 0 |
| #define MAINBOARD_POWER_ON 1 |
| |
| #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| #endif |
| |
| #define BIT0 (1 << 0) |
| #define BIT1 (1 << 1) |
| #define BIT2 (1 << 2) |
| #define BIT3 (1 << 3) |
| #define BIT4 (1 << 4) |
| #define BIT5 (1 << 5) |
| #define BIT6 (1 << 6) |
| #define BIT7 (1 << 7) |
| |
| #define BIT8 (1 << 8 ) |
| #define BIT9 (1 << 9 ) |
| #define BIT10 (1 << 10) |
| #define BIT11 (1 << 11) |
| #define BIT12 (1 << 12) |
| #define BIT13 (1 << 13) |
| #define BIT14 (1 << 14) |
| #define BIT15 (1 << 15) |
| |
| #define BIT16 (1 << 16) |
| #define BIT17 (1 << 17) |
| #define BIT18 (1 << 18) |
| #define BIT19 (1 << 19) |
| #define BIT20 (1 << 20) |
| #define BIT21 (1 << 21) |
| #define BIT22 (1 << 22) |
| #define BIT23 (1 << 23) |
| #define BIT24 (1 << 24) |
| #define BIT25 (1 << 25) |
| #define BIT26 (1 << 26) |
| #define BIT27 (1 << 27) |
| #define BIT28 (1 << 28) |
| #define BIT29 (1 << 29) |
| #define BIT30 (1 << 30) |
| #define BIT31 (1 << 31) |
| |
| /* |
| * HUDSON enables all USB controllers by default in SMBUS Control. |
| * HUDSON enables SATA by default in SMBUS Control. |
| */ |
| |
| static void sm_init(device_t dev) |
| { |
| setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); |
| } |
| |
| static int lsmbus_recv_byte(device_t dev) |
| { |
| u32 device; |
| struct resource *res; |
| struct bus *pbus; |
| |
| device = dev->path.i2c.device; |
| pbus = get_pbus_smbus(dev); |
| |
| res = find_resource(pbus->dev, 0x90); |
| |
| return do_smbus_recv_byte(res->base, device); |
| } |
| |
| static int lsmbus_send_byte(device_t dev, u8 val) |
| { |
| u32 device; |
| struct resource *res; |
| struct bus *pbus; |
| |
| device = dev->path.i2c.device; |
| pbus = get_pbus_smbus(dev); |
| |
| res = find_resource(pbus->dev, 0x90); |
| |
| return do_smbus_send_byte(res->base, device, val); |
| } |
| |
| static int lsmbus_read_byte(device_t dev, u8 address) |
| { |
| u32 device; |
| struct resource *res; |
| struct bus *pbus; |
| |
| device = dev->path.i2c.device; |
| pbus = get_pbus_smbus(dev); |
| |
| res = find_resource(pbus->dev, 0x90); |
| |
| return do_smbus_read_byte(res->base, device, address); |
| } |
| |
| static int lsmbus_write_byte(device_t dev, u8 address, u8 val) |
| { |
| u32 device; |
| struct resource *res; |
| struct bus *pbus; |
| |
| device = dev->path.i2c.device; |
| pbus = get_pbus_smbus(dev); |
| |
| res = find_resource(pbus->dev, 0x90); |
| |
| return do_smbus_write_byte(res->base, device, address, val); |
| } |
| static struct smbus_bus_operations lops_smbus_bus = { |
| .recv_byte = lsmbus_recv_byte, |
| .send_byte = lsmbus_send_byte, |
| .read_byte = lsmbus_read_byte, |
| .write_byte = lsmbus_write_byte, |
| }; |
| |
| static void hudson_sm_read_resources(device_t dev) |
| { |
| } |
| |
| static void hudson_sm_set_resources(struct device *dev) |
| { |
| } |
| |
| static struct pci_operations lops_pci = { |
| .set_subsystem = pci_dev_set_subsystem, |
| }; |
| static struct device_operations smbus_ops = { |
| .read_resources = hudson_sm_read_resources, |
| .set_resources = hudson_sm_set_resources, |
| .enable_resources = pci_dev_enable_resources, |
| .init = sm_init, |
| .scan_bus = scan_smbus, |
| .ops_pci = &lops_pci, |
| .ops_smbus_bus = &lops_smbus_bus, |
| }; |
| static const struct pci_driver smbus_driver __pci_driver = { |
| .ops = &smbus_ops, |
| .vendor = PCI_VENDOR_ID_AMD, |
| .device = PCI_DEVICE_ID_ATI_SB900_SM, |
| }; |