| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright 2014 Rockchip Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| if BOARD_GOOGLE_VEYRON_DANGER |
| |
| config BOARD_SPECIFIC_OPTIONS # dummy |
| def_bool y |
| select BOARD_ID_AUTO |
| select BOARD_ROMSIZE_KB_4096 |
| select COMMON_CBFS_SPI_WRAPPER |
| select HAVE_HARD_RESET |
| select MAINBOARD_HAS_NATIVE_VGA_INIT |
| select MAINBOARD_DO_NATIVE_VGA_INIT |
| select MAINBOARD_HAS_CHROMEOS |
| select RAM_CODE_SUPPORT |
| select SOC_ROCKCHIP_RK3288 |
| select SPI_FLASH |
| select SPI_FLASH_GIGADEVICE |
| select SPI_FLASH_WINBOND |
| select MAINBOARD_HAS_NATIVE_VGA_INIT |
| select MAINBOARD_HAS_CHROMEOS |
| |
| config CHROMEOS |
| select CHROMEOS_VBNV_FLASH |
| select PHYSICAL_REC_SWITCH |
| |
| config MAINBOARD_DIR |
| string |
| default google/veyron_danger |
| |
| config MAINBOARD_PART_NUMBER |
| string |
| default "Veyron_Danger" |
| |
| config MAINBOARD_VENDOR |
| string |
| default "Google" |
| |
| config BOOT_MEDIA_SPI_BUS |
| int |
| default 2 |
| |
| config DRIVER_TPM_I2C_BUS |
| hex |
| default 0x1 |
| |
| config DRIVER_TPM_I2C_ADDR |
| hex |
| default 0x20 |
| |
| config CONSOLE_SERIAL_UART_ADDRESS |
| hex |
| depends on DRIVERS_UART |
| default 0xFF690000 |
| |
| config PMIC_BUS |
| int |
| default 0 |
| |
| endif # BOARD_GOOGLE_VEYRON_DANGER |