| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config CPU_INTEL_SOCKET_PGA370 |
| bool |
| select CPU_INTEL_MODEL_6XX |
| select MMX |
| select UDELAY_TSC |
| |
| if CPU_INTEL_SOCKET_PGA370 |
| |
| # Not all CPUs for Socket 370 can do SSE2 |
| config SSE2 |
| bool |
| default n |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xcf000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x01000 |
| |
| endif |