| # |
| # This file is part of the coreboot project. |
| # |
| # |
| # This program is free software; you can redistribute it and/or modify |
| # it under the terms of the GNU General Public License as published by |
| # the Free Software Foundation; version 2 of the License. |
| # |
| # This program is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| # GNU General Public License for more details. |
| # |
| chip northbridge/amd/agesa/family15tn/root_complex |
| |
| device cpu_cluster 0 on |
| chip cpu/amd/agesa/family15tn |
| device lapic 10 on end |
| end |
| end |
| |
| device domain 0 on |
| subsystemid 0x1022 0x1410 inherit |
| chip northbridge/amd/agesa/family15tn # CPU side of HT root complex |
| |
| chip northbridge/amd/agesa/family15tn # PCI side of HT root complex |
| device pci 0.0 on end # Root Complex |
| device pci 2.0 on end # Internal Graphics P2P bridge 0x99XX |
| end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex |
| |
| chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus |
| device pci 10.0 on end # XHCI HC0 |
| device pci 10.1 on end # XHCI HC1 |
| device pci 11.0 on end # SATA |
| device pci 12.0 on end # USB |
| device pci 12.2 on end # USB |
| device pci 13.0 on end # USB |
| device pci 13.2 on end # USB |
| device pci 14.0 on end # SMBUS |
| device pci 14.1 off end # unused |
| device pci 14.2 on end # HDA 0x4383 |
| device pci 14.3 on # LPC 0x780e |
| chip superio/nuvoton/nct6779d |
| device pnp 2e.0 off end # FDC |
| device pnp 2e.1 off end # LPT1 |
| device pnp 2e.2 on # COM1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.3 off end # COM2/IR |
| device pnp 2e.5 off end # Keyboard |
| device pnp 2e.6 off end # CIR |
| device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 |
| io 0xe0 = 0x7f |
| io 0xe1 = 0x10 |
| io 0xe2 = 0x00 |
| io 0xe3 = 0x00 |
| io 0xe4 = 0xff |
| io 0xe5 = 0xff |
| io 0xe6 = 0xff |
| io 0xe7 = 0xff |
| io 0xec = 0x00 |
| io 0xed = 0xff |
| io 0xf4 = 0xff |
| io 0xf5 = 0xff |
| io 0xf6 = 0x00 |
| io 0xf7 = 0x00 |
| io 0xf8 = 0x00 |
| end |
| device pnp 2e.8 on # WDT1, GPIO0, GPIO1 |
| io 0x30 = 0x00 |
| io 0x60 = 0x00 |
| io 0x61 = 0x00 |
| io 0xe0 = 0xff |
| io 0xe1 = 0xff |
| io 0xe2 = 0xff |
| io 0xe3 = 0xff |
| io 0xe4 = 0xff |
| io 0xf0 = 0xff |
| io 0xf1 = 0x28 |
| io 0xf2 = 0x00 |
| io 0xf3 = 0x00 |
| io 0xf4 = 0x08 |
| io 0xf5 = 0xff |
| io 0xf6 = 0x00 |
| io 0xf7 = 0xff |
| end |
| device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 |
| io 0x30 = 0xfe |
| io 0xe0 = 0xff |
| io 0xe1 = 0x90 |
| io 0xe2 = 0x00 |
| io 0xe3 = 0x00 |
| io 0xe4 = 0x7f |
| io 0xe5 = 0x76 |
| io 0xe6 = 0x00 |
| io 0xe7 = 0x00 |
| io 0xe8 = 0x00 |
| io 0xe9 = 0x00 |
| io 0xea = 0x00 |
| io 0xeb = 0x00 |
| io 0xee = 0x00 |
| io 0xf0 = 0xff |
| io 0xf1 = 0x7b |
| io 0xf2 = 0x00 |
| io 0xf4 = 0xff |
| io 0xf5 = 0xef |
| io 0xf6 = 0x00 |
| io 0xf7 = 0x00 |
| io 0xfe = 0x00 |
| end |
| device pnp 2e.a on # ACPI |
| io 0xe6 = 0x4c |
| io 0xe7 = 0x11 |
| io 0xf2 = 0x5d |
| end |
| device pnp 2e.b on # Hardware Monitor, Front Panel LED |
| io 0x30 = 0x01 |
| io 0x60 = 0x02 |
| io 0x61 = 0x90 |
| io 0xe2 = 0x7f |
| io 0xe4 = 0xf1 |
| end |
| device pnp 2e.d off end # WDT1 |
| device pnp 2e.e off end # CIR WAKE-UP |
| device pnp 2e.f off # GPIO Push-pull/Open-drain selection |
| io 0xe6 = 7f |
| end |
| device pnp 2e.14 off # PORT80 UART |
| io 0xe0 = 0x00 |
| end |
| device pnp 2e.16 off end # Deep Sleep |
| end |
| end #device pci 14.3 # LPC |
| |
| device pci 14.4 on end # PCI bridge |
| device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806]) |
| device pci 15.0 on end # PCI bridge |
| device pci 15.1 on end # PCI bridge |
| device pci 15.2 on end # PCI bridge # Only present with the original boot firmware |
| end #chip southbridge/amd/hudson |
| |
| device pci 18.0 on end |
| device pci 18.1 on end |
| device pci 18.2 on end |
| device pci 18.3 on end |
| device pci 18.4 on end |
| device pci 18.5 on end |
| |
| register "spdAddrLookup" = " |
| { |
| { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| }" |
| |
| end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex |
| end #domain |
| end #chip northbridge/amd/agesa/family15tn/root_complex |