| # |
| # This file is part of the coreboot project. |
| # |
| # |
| # This program is free software; you can redistribute it and/or modify |
| # it under the terms of the GNU General Public License as published by |
| # the Free Software Foundation; version 2 of the License. |
| # |
| # This program is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| # GNU General Public License for more details. |
| # |
| chip northbridge/amd/agesa/family15tn/root_complex |
| |
| device cpu_cluster 0 on |
| chip cpu/amd/agesa/family15tn |
| device lapic 10 on end |
| end |
| end |
| |
| device domain 0 on |
| subsystemid 0x1022 0x1410 inherit |
| chip northbridge/amd/agesa/family15tn # CPU side of HT root complex |
| |
| chip northbridge/amd/agesa/family15tn # PCI side of HT root complex |
| device pci 0.0 on end # Root Complex |
| device pci 0.2 on end # IOMMU |
| device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX |
| device pci 1.1 on end # Internal Multimedia |
| device pci 2.0 on end # PCIE SLOT0 x16 blue |
| device pci 3.0 off end # unused? |
| device pci 4.0 on end # PCIE 4x black |
| device pci 5.0 off end # unused? |
| device pci 6.0 off end # unused? |
| device pci 7.0 off end # LAN |
| device pci 8.0 off end # NB/SB Link P2P bridge |
| end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex |
| |
| chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus |
| device pci 10.0 on end # XHCI HC0 |
| device pci 10.1 on end # XHCI HC1 |
| device pci 11.0 on end # SATA |
| device pci 12.0 on end # USB |
| device pci 12.2 on end # USB |
| device pci 13.0 on end # USB |
| device pci 13.2 on end # USB |
| device pci 14.0 on end # SMBUS |
| device pci 14.1 off end # IDE 0x439c |
| device pci 14.2 on end # HDA 0x4383 |
| device pci 14.3 on # LPC 0x439d |
| chip superio/ite/it8728f |
| register "TMPIN1.mode" = "THERMAL_RESISTOR" |
| register "TMPIN2.mode" = "THERMAL_RESISTOR" |
| register "TMPIN3.mode" = "THERMAL_RESISTOR" |
| |
| register "FAN1.mode" = "FAN_SMART_AUTOMATIC" |
| register "FAN1.smart.tmpin" = "1" |
| register "FAN1.smart.tmp_off" = "0x80" # never |
| register "FAN1.smart.tmp_start" = "20" |
| register "FAN1.smart.tmp_full" = "70" |
| register "FAN1.smart.tmp_delta" = "0" |
| register "FAN1.smart.smoothing" = "1" |
| register "FAN1.smart.pwm_start" = "20" |
| register "FAN1.smart.slope" = "32" |
| |
| # Enable tacho reading for chassis fan. |
| register "FAN2.mode" = "FAN_MODE_OFF" |
| |
| device pnp 2e.0 off # Floppy |
| io 0x60 = 0x3f0 |
| irq 0x70 = 6 |
| drq 0x74 = 2 |
| end |
| device pnp 2e.1 on # Com1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.2 off # Com2 |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.3 off # Parallel Port |
| io 0x60 = 0x378 |
| irq 0x70 = 7 |
| end |
| device pnp 2e.4 on # Env Controller |
| io 0x60 = 0x290 |
| io 0x62 = 0x220 |
| irq 0x70 = 0 |
| end |
| device pnp 2e.5 on # Keyboard |
| io 0x60 = 0x60 |
| io 0x62 = 0x64 |
| irq 0x70 = 1 |
| end |
| device pnp 2e.6 off # Mouse |
| irq 0x70 = 12 |
| end |
| device pnp 2e.7 on # GPIO |
| io 0x60 = 0x228 #SMI |
| io 0x62 = 0x300 #Simple I/O |
| io 0x64 = 0x238 #Phony resource IT8603E does not have it |
| irq 0x70 = 0 |
| end |
| device pnp 2e.a off end # CIR |
| end #superio/ite/it8728f |
| end #device pci 14.3 # LPC |
| device pci 14.4 on end # PCI 0x4384 |
| device pci 14.5 on end # USB 2 |
| device pci 14.6 off end # Gec |
| device pci 14.7 off end # SD |
| device pci 15.0 on end # PCIe 0 - onboard PCIe 1x |
| device pci 15.1 on end # PCIe 1 onboard gigabit |
| device pci 15.2 off end # unused |
| device pci 15.3 off end # unused |
| end #chip southbridge/amd/agesa/hudson |
| |
| device pci 18.0 on end |
| device pci 18.1 on end |
| device pci 18.2 on end |
| device pci 18.3 on end |
| device pci 18.4 on end |
| device pci 18.5 on end |
| |
| register "spdAddrLookup" = " |
| { |
| { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| }" |
| |
| end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex |
| end #domain |
| end #chip northbridge/amd/agesa/family15tn/root_complex |