blob: 6657fa9f29bf87e98e0f8c3148ef8cd048f3b55b [file] [log] [blame]
# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake
# Enable Root port 1..4 (COMe 4..7), 12 (COMe 3)
register "PcieRpEnable[ 0]" = "1"
register "PcieRpEnable[ 1]" = "1"
register "PcieRpEnable[ 2]" = "1"
register "PcieRpEnable[ 3]" = "1"
register "PcieRpEnable[11]" = "1"
register "SataPortsEnable[3]" = "1"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[5] = USB2_PORT_LONG(OC2),
[6] = USB2_PORT_LONG(OC3),
[7] = USB2_PORT_LONG(OC3),
[8] = USB2_PORT_MID(OC4),
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0),
[1] = USB3_PORT_DEFAULT(OC0),
[2] = USB3_PORT_DEFAULT(OC1),
[3] = USB3_PORT_DEFAULT(OC1),
}"
end
device ref pcie_rp1 on end
device ref pcie_rp2 on end
device ref pcie_rp3 on end
device ref pcie_rp4 on end
device ref pcie_rp12 on end
device ref smbus on
chip drivers/i2c/nct7802y
register "peci[0]" = "{ PECI_DOMAIN_0, 100 }"
register "fan[1].mode" = "FAN_SMART"
register "fan[1].smart.mode" = "SMART_FAN_DUTY"
register "fan[1].smart.tempsrc" = "TEMP_SOURCE_PECI_0"
register "fan[1].smart.table" = "{ { 30, 40 },
{ 40, 48 },
{ 50, 60 },
{ 60, 76 } }"
register "fan[1].smart.critical_temp" = "80"
device i2c 0x2e on end
end
end
end
end