skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
index 29252fe..1b553d1 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -11,31 +11,32 @@
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
- register "usb2_ports" = "{
- [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
- [1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */
- [2] = USB2_PORT_MID(OC1), /* USB 3 */
- [3] = USB2_PORT_MID(OC1), /* USB 2 */
- [4] = USB2_PORT_MID(OC2), /* USB 1 */
- [5] = USB2_PORT_MID(OC2), /* USB 0 */
- [6] = USB2_PORT_MID(OC0), /* USB 5 */
- [7] = USB2_PORT_MID(OC0), /* USB 4 */
- [8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */
- [9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
- [10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
- [11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
- }"
-
- register "usb3_ports" = "{
- [0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
- [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
- [2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
- [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
- [4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */
- }"
-
device domain 0 on
subsystemid 0x15d9 0x0896 inherit
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
+ [1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */
+ [2] = USB2_PORT_MID(OC1), /* USB 3 */
+ [3] = USB2_PORT_MID(OC1), /* USB 2 */
+ [4] = USB2_PORT_MID(OC2), /* USB 1 */
+ [5] = USB2_PORT_MID(OC2), /* USB 0 */
+ [6] = USB2_PORT_MID(OC0), /* USB 5 */
+ [7] = USB2_PORT_MID(OC0), /* USB 4 */
+ [8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */
+ [9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
+ [10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
+ [11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
+ [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
+ [2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
+ [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
+ [4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */
+ }"
+ end
device ref peg0 on
# Slot JPCIE6
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"