skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index b7c4395..81557eb 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -74,26 +74,6 @@
# RP10, uses CLK SRC 4
register "PcieRpClkSrcNumber[9]" = "4"
- register "usb2_ports" = "{
- [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
- [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
- [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
- [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */
- [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
- [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
- [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
- [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
- [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */
- [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
- [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
- }"
-
- register "usb3_ports" = "{
- [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
- [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
- [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
- [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
- }"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
@@ -113,6 +93,28 @@
}"
device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
+ [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
+ [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
+ [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */
+ [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
+ [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
+ [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
+ [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
+ [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */
+ [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
+ [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
+ [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
+ }"
+ end
device ref imgu on end
device ref cio on end
device ref pcie_rp1 on end # x4 SLOT1