| ## SPDX-License-Identifier: GPL-2.0-only |
| |
| config SOUTHBRIDGE_INTEL_LYNXPOINT |
| bool |
| |
| if SOUTHBRIDGE_INTEL_LYNXPOINT |
| |
| config SOUTH_BRIDGE_OPTIONS |
| def_bool y |
| select ACPI_COMMON_MADT_IOAPIC |
| select ACPI_COMMON_MADT_LAPIC |
| select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| select ACPI_SOC_NVS |
| select AZALIA_PLUGIN_SUPPORT |
| select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS |
| select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 |
| select SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
| select SOUTHBRIDGE_INTEL_COMMON_PMCLIB |
| select SOUTHBRIDGE_INTEL_COMMON_PMBASE |
| select SOUTHBRIDGE_INTEL_COMMON_RTC |
| select SOUTHBRIDGE_INTEL_COMMON_RESET |
| select HAVE_SMI_HANDLER |
| select HAVE_USBDEBUG_OPTIONS |
| select USE_WATCHDOG_ON_BOOT |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select INTEL_DESCRIPTOR_MODE_CAPABLE |
| select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT |
| select RTC |
| select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP |
| select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
| select HAVE_INTEL_CHIPSET_LOCKDOWN |
| select HAVE_POWER_STATE_AFTER_FAILURE |
| select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
| select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG |
| select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG |
| select TCO_SPACE_NOT_YET_SPLIT |
| |
| config INTEL_LYNXPOINT_LP |
| bool |
| default n |
| help |
| Set this option to y for LynxPoint LP (Haswell ULT). |
| |
| config EHCI_BAR |
| hex |
| default 0xd8000000 if USE_BROADWELL_MRC |
| default 0xe8000000 |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default n |
| help |
| If you set this option to y, the serial IRQ machine will be |
| operated in continuous mode. |
| |
| config HPET_MIN_TICKS |
| default 0x80 |
| |
| config FINALIZE_USB_ROUTE_XHCI |
| bool "Route all ports to XHCI controller in finalize step" |
| default y |
| help |
| If you set this option to y, the USB ports will be routed |
| to the XHCI controller during the finalize SMM callback. |
| |
| config PCIEXP_AER |
| bool |
| default y |
| |
| config PCIEXP_CLK_PM |
| default y |
| |
| config PCIEXP_L1_SUB_STATE |
| default y |
| |
| config SERIALIO_UART_CONSOLE |
| bool "Use SerialIO UART for console" |
| depends on INTEL_LYNXPOINT_LP |
| select DRIVERS_UART_8250MEM_32 |
| help |
| Selected by mainboards where SerialIO UARTs can be used to retrieve |
| coreboot logs. Boards also need to set UART_FOR_CONSOLE accordingly. |
| |
| config CONSOLE_UART_BASE_ADDRESS |
| default 0xd6000000 if SERIALIO_UART_CONSOLE |
| |
| config DISABLE_ME_PCI |
| bool "Disable Intel ME PCI interface (MEI1)" |
| default y |
| help |
| Disable and hide the ME PCI interface during finalize stage of boot. |
| This will prevent the OS (and userspace apps) from interacting with |
| the ME via the PCI interface after boot. |
| |
| endif |