| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2008-2009 coresystems GmbH |
| * Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org> |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; version 2 of |
| * the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <device/pci_ops.h> |
| #include <device/pci_def.h> |
| #include <northbridge/intel/sandybridge/sandybridge.h> |
| #include <northbridge/intel/sandybridge/raminit_native.h> |
| #include <southbridge/intel/bd82x6x/pch.h> |
| #include <southbridge/intel/common/gpio.h> |
| |
| void pch_enable_lpc(void) |
| { |
| /* EC Decode Range Port60/64, Port62/66 */ |
| /* Enable EC, PS/2 Keyboard/Mouse, LPT */ |
| pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | |
| LPT_LPC_EN); |
| } |
| |
| void mainboard_rcba_config(void) |
| { |
| } |
| |
| const struct southbridge_usb_port mainboard_usb_ports[] = { |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| { 1, 0, -1 }, |
| }; |
| |
| void mainboard_early_init(int s3resume) |
| { |
| } |
| |
| void mainboard_config_superio(void) |
| { |
| } |
| |
| void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| { |
| read_spd(&spd[0], 0x50, id_only); |
| read_spd(&spd[2], 0x52, id_only); |
| } |