sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c
index 6fee17ab..d04582d 100644
--- a/src/mainboard/apple/macbookair4_2/romstage.c
+++ b/src/mainboard/apple/macbookair4_2/romstage.c
@@ -23,10 +23,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
}
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index 6d0b3af..6c3d980 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -33,12 +33,6 @@
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
- /* Map 1 byte to the LPC bus. */
- pci_write_config32(dev, LPC_GEN1_DEC, 0x00164d);
-
- /* Map a range for the runtime_port registers to the LPC bus. */
- pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
-
#if CONFIG(DRIVERS_UART_8250IO)
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 67bcbcb..b35a8b4 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -30,7 +30,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index d34b1e4..844f754 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -33,13 +33,6 @@
/* EC Decode Range Port60/64 and Port62/66 */
/* Enable EC and PS/2 Keyboard/Mouse*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
-
- /* EC Decode Range Port68/6C */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001);
-
- /* EC Decode Range Port 380-387 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001);
-
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 8da1308..2f3f07c 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -34,28 +34,12 @@
void pch_enable_lpc(void)
{
- const struct device *lpc;
- const struct southbridge_intel_bd82x6x_config *config = NULL;
-
- lpc = pcidev_on_root(0x1f, 0);
- if (!lpc)
- return;
- if (lpc->chip_info)
- config = lpc->chip_info;
- if (!config)
- return;
-
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
GAMEL_LPC_EN | COMA_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 76a4b4b..ac06fbc 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -31,12 +31,6 @@
/* Parrot EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
-
- /* Map EC_IO decode to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001);
-
- /* Map EC registers 68/6C decode to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 7539dd7..6690c68 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -41,9 +41,6 @@
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
CNF1_LPC_EN | FDD_LPC_EN);
-
- /* Stout EC Decode Range Port68/6C */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb
index 585d61d..79a84b7 100644
--- a/src/mainboard/hp/2570p/devicetree.cb
+++ b/src/mainboard/hp/2570p/devicetree.cb
@@ -46,6 +46,7 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c
index 21e3cea..6401909 100644
--- a/src/mainboard/hp/2570p/romstage.c
+++ b/src/mainboard/hp/2570p/romstage.c
@@ -28,8 +28,6 @@
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb
index 515d20f..a301857 100644
--- a/src/mainboard/hp/2760p/devicetree.cb
+++ b/src/mainboard/hp/2760p/devicetree.cb
@@ -55,6 +55,7 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
index 68af61b..ba6f956 100644
--- a/src/mainboard/hp/2760p/romstage.c
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -27,8 +27,6 @@
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb
index 79259b4..a06aea9 100644
--- a/src/mainboard/hp/8460p/devicetree.cb
+++ b/src/mainboard/hp/8460p/devicetree.cb
@@ -54,6 +54,7 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
index a3fb5f0..f30c3a8 100644
--- a/src/mainboard/hp/8460p/romstage.c
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -34,8 +34,6 @@
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb
index 2a115cc..4715372 100644
--- a/src/mainboard/hp/8470p/devicetree.cb
+++ b/src/mainboard/hp/8470p/devicetree.cb
@@ -55,6 +55,7 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c
index a876173..b1375e8 100644
--- a/src/mainboard/hp/8470p/romstage.c
+++ b/src/mainboard/hp/8470p/romstage.c
@@ -33,8 +33,6 @@
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb
index 7d74c94..d98402c 100644
--- a/src/mainboard/hp/8770w/devicetree.cb
+++ b/src/mainboard/hp/8770w/devicetree.cb
@@ -43,6 +43,7 @@
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c
index a7f6b22..8956b08 100644
--- a/src/mainboard/hp/8770w/romstage.c
+++ b/src/mainboard/hp/8770w/romstage.c
@@ -34,8 +34,6 @@
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb
index 5d4e5b8..d626934 100644
--- a/src/mainboard/hp/folio_9470m/devicetree.cb
+++ b/src/mainboard/hp/folio_9470m/devicetree.cb
@@ -46,6 +46,7 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c
index db3296c..8ff7813 100644
--- a/src/mainboard/hp/folio_9470m/romstage.c
+++ b/src/mainboard/hp/folio_9470m/romstage.c
@@ -30,8 +30,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb
index 4d0d639..ad69ca2 100644
--- a/src/mainboard/hp/revolve_810_g1/devicetree.cb
+++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb
@@ -46,6 +46,7 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c
index f62024c..5f8df63 100644
--- a/src/mainboard/hp/revolve_810_g1/romstage.c
+++ b/src/mainboard/hp/revolve_810_g1/romstage.c
@@ -33,8 +33,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 60072b0..4ed1f3c 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -44,8 +44,11 @@
register "sata_port_map" = "0x3f"
+ register "gen1_dec" = "0x00fc1601"
+ # runtime_port registers
+ register "gen2_dec" = "0x000c0181"
# SuperIO range is 0x700-0x73f
- register "gen2_dec" = "0x003c0701"
+ register "gen3_dec" = "0x003c0701"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9a9fc24..a28ae78 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -39,12 +39,6 @@
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
- /* Map 256 bytes at 0x1600 to the LPC bus. */
- pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601);
-
- /* Map a range for the runtime_port registers to the LPC bus. */
- pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
-
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {
pci_write_config16(dev, LPC_EN,
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index c8003ae..426ac4e 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -29,10 +29,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index 32a3cc2..dd8fc17 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -30,9 +30,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index 806c72a..ebf5aed 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -56,10 +56,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 9c51713..49de58d 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -56,10 +56,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
index db50bb3..1f4b90d 100644
--- a/src/mainboard/lenovo/t430/romstage.c
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -55,9 +55,6 @@
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC,
- (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index 4edd5c6..e590bb6 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -26,10 +26,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index ebff37f..5c23b8e 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -58,10 +58,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 24e2d9c..67cf97c 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -58,10 +58,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c
index ea550aa..79a2276 100644
--- a/src/mainboard/lenovo/x131e/romstage.c
+++ b/src/mainboard/lenovo/x131e/romstage.c
@@ -26,11 +26,6 @@
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index a951fbc..f666671 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -35,10 +35,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 5f9a931..9ecb8a3 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -34,10 +34,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 3f31141..10cddeb 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -31,10 +31,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 7199473..feae5bf 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -61,6 +61,7 @@
# EC range is 0xa00-0xa3f
register "gen1_dec" = "0x003c0a01"
register "gen2_dec" = "0x003c0b01"
+ register "gen3_dec" = "0x00fc1601"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index a77149d..d4b6dd8 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -43,9 +43,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
- /* map full 256 bytes at 0x1600 to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
-
try_enabling_LPC47N207_uart();
#else
/* Enable SuperIO + EC + KBC */
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 192e63d..060fc40 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -50,6 +50,7 @@
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
+ register "gen1_dec" = "0x00fc1601"
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index a8e28d6..77fd160 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -55,9 +55,6 @@
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
CNF2_LPC_EN | COMA_LPC_EN);
- /* map full 256 bytes at 0x1600 to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
-
try_enabling_LPC47N207_uart();
#else
/* Enable SuperIO + PS/2 Keyboard/Mouse */
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
index 9a67ab2..c7d8f0f 100644
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -24,10 +24,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
}
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index e74c304..4f9cd32 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -27,6 +27,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
+#include "chip.h"
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
@@ -258,10 +259,31 @@
write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */
}
+static void pch_enable_lpc_gen_decode(void)
+{
+ const struct device *dev = pcidev_on_root(0x1f, 0);
+ const struct southbridge_intel_bd82x6x_config *config = NULL;
+
+ /* Set up generic decode ranges */
+ if (!dev)
+ return;
+ if (dev->chip_info)
+ config = dev->chip_info;
+ if (!config)
+ return;
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
+}
+
void early_pch_init(void)
{
pch_enable_lpc();
+ pch_enable_lpc_gen_decode();
+
pch_enable_bars();
pch_generic_setup();
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index e93704e..141ec5c 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -28,7 +28,7 @@
}
for i := uint(0); i < max; i++ {
- if ((constraint>>i)&1 == 1) {
+ if (constraint>>i)&1 == 1 {
fmt.Fprintf(sb, " .gpio%d = %s,\n",
(set-1)*32+i,
bits[partno][(val>>i)&1])
@@ -236,8 +236,8 @@
"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
"c2_latency": FormatHexLE16(FADT[96:98]),
"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
- "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
- "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4] &^ (1 << 23)),
+ "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
+ "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)),
},
PCISlots: []PCISlot{
PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
@@ -315,10 +315,6 @@
{
`)
RestorePCI16Simple(sb, addr, 0x82)
- RestorePCI32Simple(sb, addr, 0x84)
- RestorePCI32Simple(sb, addr, 0x88)
- RestorePCI32Simple(sb, addr, 0x8c)
- RestorePCI32Simple(sb, addr, 0x90)
RestorePCI16Simple(sb, addr, 0x80)