commit 6b688f5329e560ef432f6ea281b2fe3d905ef297
author Patrick Georgi <pgeorgi@google.com> Fri Feb 12 13:49:11 2021 +0100
committer Patrick Georgi <pgeorgi@google.com> Mon Feb 15 11:30:40 2021 +0000
tree 831ff654f7477b293421e38b8ed880f2cc740386
parent 036d66be051c4aeeac3b6220974e93645489c27d

src: use ARRAY_SIZE where possible

Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c

diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
index b1ac093..a58e918 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
@@ -110,8 +110,8 @@
 
 CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN  = {
   &PcieInitEarlyTable[0],
-  sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(PcieInitEarlyTable)
+  };
 
 STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
   {
@@ -160,8 +160,8 @@
 
 CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN  = {
   &CoreInitTable[0],
-  sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(CoreInitTable)
+  };
 
 
 STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
@@ -208,8 +208,8 @@
 
 CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN  = {
   &PortInitEarlyTable[0],
-  sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(PortInitEarlyTable)
+  };
 
 
 STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
@@ -227,5 +227,5 @@
 
 CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN  = {
   &PortInitMidTable[0],
-  sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(PortInitMidTable)
+  };