zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe late post initialization. |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 65061 $ @e \$Date: 2012-02-06 23:48:39 -0600 (Mon, 06 Feb 2012) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | #include "AGESA.h" |
| 50 | #include "Gnb.h" |
| 51 | #include "GnbPcie.h" |
| 52 | #include "PcieComplexDataTN.h" |
| 53 | #include "GnbRegistersTN.h" |
| 54 | |
| 55 | /*---------------------------------------------------------------------------------------- |
| 56 | * D E F I N I T I O N S A N D M A C R O S |
| 57 | *---------------------------------------------------------------------------------------- |
| 58 | */ |
| 59 | |
| 60 | |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * T Y P E D E F S A N D S T R U C T U R E S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | |
| 67 | /*---------------------------------------------------------------------------------------- |
| 68 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 69 | *---------------------------------------------------------------------------------------- |
| 70 | */ |
| 71 | |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * T A B L E S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { |
| 79 | { |
| 80 | WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), |
| 81 | D0F0xE4_WRAP_8016_CalibAckLatency_MASK, |
| 82 | 0 |
| 83 | }, |
| 84 | { |
| 85 | PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), |
| 86 | D0F0xE4_PHY_2008_VdDetectEn_MASK, |
| 87 | 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET |
| 88 | }, |
| 89 | { |
| 90 | PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), |
| 91 | D0F0xE4_PHY_2008_VdDetectEn_MASK, |
| 92 | 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET |
| 93 | }, |
| 94 | { |
| 95 | PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS), |
| 96 | D0F0xE4_PHY_2008_VdDetectEn_MASK, |
| 97 | 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET |
| 98 | }, |
| 99 | { |
| 100 | PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), |
| 101 | D0F0xE4_PHY_2008_VdDetectEn_MASK, |
| 102 | 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET |
| 103 | }, |
| 104 | { |
| 105 | PHY_SPACE (DDI2_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), |
| 106 | D0F0xE4_PHY_2008_VdDetectEn_MASK, |
| 107 | 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET |
| 108 | } |
| 109 | }; |
| 110 | |
| 111 | CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN = { |
| 112 | &PcieInitEarlyTable[0], |
| 113 | sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) |
| 114 | }; |
| 115 | |
| 116 | STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { |
| 117 | { |
| 118 | D0F0xE4_CORE_0020_ADDRESS, |
| 119 | D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | |
| 120 | D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK, |
| 121 | (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) |
| 122 | }, |
| 123 | { |
| 124 | D0F0xE4_CORE_0010_ADDRESS, |
| 125 | D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK, |
| 126 | (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET) |
| 127 | }, |
| 128 | { |
| 129 | D0F0xE4_CORE_001C_ADDRESS, |
| 130 | D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | |
| 131 | D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | |
| 132 | D0F0xE4_CORE_001C_TxArbMstLimit_MASK, |
| 133 | (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | |
| 134 | (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | |
| 135 | (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) |
| 136 | }, |
| 137 | { |
| 138 | D0F0xE4_CORE_0040_ADDRESS, |
| 139 | D0F0xE4_CORE_0040_PElecIdleMode_MASK, |
| 140 | (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) |
| 141 | }, |
| 142 | { |
| 143 | D0F0xE4_CORE_0002_ADDRESS, |
| 144 | D0F0xE4_CORE_0002_HwDebug_0__MASK, |
| 145 | (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET) |
| 146 | }, |
| 147 | { |
| 148 | D0F0xE4_CORE_00C1_ADDRESS, |
| 149 | D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | |
| 150 | D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, |
| 151 | (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | |
| 152 | (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) |
| 153 | }, |
| 154 | { |
| 155 | D0F0xE4_CORE_00B0_ADDRESS, |
| 156 | D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK, |
| 157 | (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) |
| 158 | } |
| 159 | }; |
| 160 | |
| 161 | CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN = { |
| 162 | &CoreInitTable[0], |
| 163 | sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) |
| 164 | }; |
| 165 | |
| 166 | |
| 167 | STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { |
| 168 | { |
| 169 | DxF0xE4_x02_ADDRESS, |
| 170 | DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, |
| 171 | (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET) |
| 172 | }, |
| 173 | { |
| 174 | DxF0xE4_x70_ADDRESS, |
| 175 | DxF0xE4_x70_RxRcbCplTimeoutMode_MASK, |
| 176 | (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET) |
| 177 | }, |
| 178 | { |
| 179 | DxF0xE4_xA0_ADDRESS, |
| 180 | DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK | DxF0xE4_xA0_LcL0sInactivity_MASK, |
| 181 | (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) | |
| 182 | (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) | |
| 183 | (0x6 << DxF0xE4_xA0_LcL0sInactivity_OFFSET) |
| 184 | }, |
| 185 | { |
| 186 | DxF0xE4_xA1_ADDRESS, |
| 187 | DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK, |
| 188 | (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) |
| 189 | }, |
| 190 | { |
| 191 | DxF0xE4_xA2_ADDRESS, |
| 192 | DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK, |
| 193 | (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) | |
| 194 | (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET) |
| 195 | }, |
| 196 | { |
| 197 | DxF0xE4_xA3_ADDRESS, |
| 198 | DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK, |
| 199 | (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) |
| 200 | }, |
| 201 | { |
| 202 | DxF0xE4_xB1_ADDRESS, |
| 203 | DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK, |
| 204 | (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) | |
| 205 | (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET) |
| 206 | } |
| 207 | }; |
| 208 | |
| 209 | CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN = { |
| 210 | &PortInitEarlyTable[0], |
| 211 | sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) |
| 212 | }; |
| 213 | |
| 214 | |
| 215 | STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { |
| 216 | { |
| 217 | DxF0xE4_xA2_ADDRESS, |
| 218 | DxF0xE4_xA2_LcDynLanesPwrState_MASK, |
| 219 | (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) |
| 220 | }, |
| 221 | { |
| 222 | DxF0xE4_xC0_ADDRESS, |
| 223 | DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, |
| 224 | (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) |
| 225 | } |
| 226 | }; |
| 227 | |
| 228 | CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN = { |
| 229 | &PortInitMidTable[0], |
| 230 | sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) |
| 231 | }; |