| commit | 6b688f5329e560ef432f6ea281b2fe3d905ef297 | [log] [tgz] |
|---|---|---|
| author | Patrick Georgi <pgeorgi@google.com> | Fri Feb 12 13:49:11 2021 +0100 |
| committer | Patrick Georgi <pgeorgi@google.com> | Mon Feb 15 11:30:40 2021 +0000 |
| tree | 831ff654f7477b293421e38b8ed880f2cc740386 | |
| parent | 036d66be051c4aeeac3b6220974e93645489c27d [diff] [blame] |
src: use ARRAY_SIZE where possible Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index ae0cce3..5c10dd5 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c
@@ -20,7 +20,7 @@ { msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - if ((clk_info.lo & 0xf) < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int))) + if ((clk_info.lo & 0xf) < ARRAY_SIZE(cpu_bus_clk_freq_table)) return cpu_bus_clk_freq_table[clk_info.lo & 0xf]; return 0;