src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb

chip soc/intel/cannonlake

	device cpu_cluster 0 on end

	# Enable eDP device
	register "DdiPortEdp" = "1"
	# Enable HPD for DDI ports B/C
	register "DdiPortBHpd" = "1"
	register "DdiPortCHpd" = "1"
	register "DdiPortDHpd" = "1"
	register "DdiPortFHpd" = "1"
	# Enable DDC for DDI ports B/C
	register "DdiPortBDdc" = "1"
	register "DdiPortCDdc" = "1"
	register "DdiPortDDdc" = "1"
	register "DdiPortFDdc" = "1"

	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
		[PchSerialIoIndexSPI0] = PchSerialIoPci,
		[PchSerialIoIndexSPI1] = PchSerialIoPci,
		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
	}"

	register "SataSalpSupport" = "1"
	register "SataPortsEnable[0]" = "1"
	register "SataPortsEnable[1]" = "1"
	register "SataPortsEnable[2]" = "1"
	register "SataPortsEnable[3]" = "1"
	register "SataPortsEnable[4]" = "1"
	register "SataPortsEnable[5]" = "1"
	register "SataPortsEnable[6]" = "1"
	register "SataPortsEnable[7]" = "1"

	register "PchHdaDspEnable" = "1"
	register "PchHdaAudioLinkHda" = "1"

	register "PcieRpEnable[0]" = "1"
	register "PcieRpEnable[1]" = "1"
	register "PcieRpEnable[2]" = "1"
	register "PcieRpEnable[3]" = "1"
	register "PcieRpEnable[4]" = "1"
	register "PcieRpEnable[5]" = "0"
	register "PcieRpEnable[6]" = "0"
	register "PcieRpEnable[7]" = "0"
	register "PcieRpEnable[8]" = "1"
	register "PcieRpEnable[9]" = "0"
	register "PcieRpEnable[10]" = "0"
	register "PcieRpEnable[11]" = "0"
	register "PcieRpEnable[12]" = "0"
	register "PcieRpEnable[13]" = "0"
	register "PcieRpEnable[14]" = "0"
	register "PcieRpEnable[15]" = "0"

	register "PcieClkSrcUsage[0]" = "1"
	register "PcieClkSrcUsage[1]" = "8"
	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
	register "PcieClkSrcUsage[3]" = "13"
	register "PcieClkSrcUsage[4]" = "4"
	register "PcieClkSrcUsage[5]" = "14"

	register "PcieClkSrcClkReq[0]" = "0"
	register "PcieClkSrcClkReq[1]" = "1"
	register "PcieClkSrcClkReq[2]" = "2"
	register "PcieClkSrcClkReq[3]" = "3"
	register "PcieClkSrcClkReq[4]" = "4"
	register "PcieClkSrcClkReq[5]" = "5"

	# GPIO for SD card detect
	register "sdcard_cd_gpio" = "GPP_G5"

	device domain 0 on
		device pci 14.3 on
			chip drivers/wifi/generic
				register "wake" = "PME_B0_EN_BIT"
				device generic 0 on end
			end
		end # CNVi wifi
		device pci 14.5 on  end # SDCard
		device pci 15.0 on  end # I2C #0
		device pci 15.1 on  end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 17.0 on  end # SATA
		device pci 19.0 on  end # I2C #4
		device pci 19.1 off end # I2C #5
		device pci 19.2 on  end # UART #2
		device pci 1a.0 on  end # eMMC
		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
			register "PcieRpSlotImplemented[0]" = "1"
		end
		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
			register "PcieRpSlotImplemented[4]" = "1"
		end
		device pci 1c.5 off end # PCI Express Port 6
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 off end # PCI Express Port 8
		device pci 1d.0 on	# PCI Express Port 9
			register "PcieRpSlotImplemented[8]" = "1"
		end
		device pci 1d.1 off end # PCI Express Port 10
		device pci 1d.2 off end # PCI Express Port 11
		device pci 1d.3 off end # PCI Express Port 12
		device pci 1d.4 off end # PCI Express Port 13
		device pci 1d.5 off end # PCI Express Port 14
		device pci 1d.6 off end # PCI Express Port 15
		device pci 1d.7 off end # PCI Express Port 16
		device pci 1e.1 off end # UART #1
		device pci 1f.6 on  end # GbE
	end
end