| chip soc/intel/cannonlake |
| |
| device cpu_cluster 0 on end |
| |
| # FSP configuration |
| register "RMT" = "1" |
| |
| register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" |
| register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" |
| register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" |
| register "usb2_ports[3]" = "USB2_PORT_MID(OC5)" |
| register "usb2_ports[4]" = "USB2_PORT_MID(OC5)" |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" |
| register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" |
| register "usb2_ports[10]" = "USB2_PORT_MID(OC3)" |
| register "usb2_ports[11]" = "USB2_PORT_MID(OC6)" |
| register "usb2_ports[12]" = "USB2_PORT_MID(OC6)" |
| |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" |
| register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" |
| register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" |
| register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" |
| register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" |
| register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)" |
| register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)" |
| register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC3)" |
| |
| register "SataSalpSupport" = "1" |
| register "SataPortsEnable[0]" = "1" |
| register "SataPortsEnable[1]" = "1" |
| register "SataPortsEnable[2]" = "1" |
| register "SataPortsEnable[3]" = "1" |
| register "SataPortsEnable[4]" = "1" |
| register "SataPortsEnable[5]" = "1" |
| register "SataPortsEnable[6]" = "1" |
| register "SataPortsEnable[7]" = "1" |
| |
| register "PchHdaDspEnable" = "0" |
| register "PchHdaAudioLinkHda" = "1" |
| |
| register "PcieRpEnable[0]" = "1" |
| register "PcieRpEnable[1]" = "1" |
| register "PcieRpEnable[2]" = "1" |
| register "PcieRpEnable[3]" = "1" |
| register "PcieRpEnable[4]" = "1" |
| register "PcieRpEnable[5]" = "0" |
| register "PcieRpEnable[6]" = "0" |
| register "PcieRpEnable[7]" = "0" |
| register "PcieRpEnable[8]" = "1" |
| register "PcieRpEnable[9]" = "0" |
| register "PcieRpEnable[10]" = "0" |
| register "PcieRpEnable[11]" = "0" |
| register "PcieRpEnable[12]" = "0" |
| register "PcieRpEnable[13]" = "0" |
| register "PcieRpEnable[14]" = "0" |
| register "PcieRpEnable[15]" = "0" |
| register "PcieRpEnable[16]" = "1" |
| register "PcieRpEnable[17]" = "1" |
| register "PcieRpEnable[18]" = "1" |
| register "PcieRpEnable[19]" = "1" |
| register "PcieRpEnable[20]" = "1" |
| register "PcieRpEnable[21]" = "1" |
| register "PcieRpEnable[22]" = "1" |
| register "PcieRpEnable[23]" = "1" |
| |
| register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" |
| register "PcieClkSrcUsage[1]" = "8" |
| register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" |
| register "PcieClkSrcUsage[3]" = "0x6" |
| register "PcieClkSrcUsage[4]" = "0x18" |
| register "PcieClkSrcUsage[5]" = "1" |
| register "PcieClkSrcUsage[6]" = "0x8" |
| register "PcieClkSrcUsage[8]" = "0x40" |
| register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED" |
| register "PcieClkSrcUsage[10]" = "0x14" |
| |
| register "PcieClkSrcClkReq[0]" = "0" |
| register "PcieClkSrcClkReq[1]" = "1" |
| register "PcieClkSrcClkReq[2]" = "2" |
| register "PcieClkSrcClkReq[3]" = "3" |
| register "PcieClkSrcClkReq[4]" = "4" |
| register "PcieClkSrcClkReq[5]" = "5" |
| register "PcieClkSrcClkReq[6]" = "6" |
| register "PcieClkSrcClkReq[8]" = "8" |
| register "PcieClkSrcClkReq[9]" = "9" |
| register "PcieClkSrcClkReq[10]" = "10" |
| |
| device domain 0 on |
| device pci 14.3 on |
| chip drivers/wifi/generic |
| register "wake" = "PME_B0_EN_BIT" |
| device generic 0 on end |
| end |
| end # CNVi wifi |
| device pci 15.0 on end # I2C #0 |
| device pci 15.1 on end # I2C #1 |
| device pci 15.2 on end # I2C #2 |
| device pci 15.3 on end # I2C #3 |
| device pci 17.0 on end # SATA |
| device pci 19.0 off end # I2C #4 (Not available on PCH-H) |
| device pci 19.1 off end # I2C #5 (Not available on PCH-H) |
| device pci 19.2 on end # UART #2 |
| device pci 1a.0 on end # eMMC |
| device pci 1c.0 on # PCI Express Port 1 |
| register "PcieRpSlotImplemented[0]" = "1" |
| end |
| device pci 1c.4 on # PCI Express Port 5 |
| register "PcieRpSlotImplemented[4]" = "1" |
| end |
| device pci 1c.5 off end # PCI Express Port 6 |
| device pci 1c.6 off end # PCI Express Port 7 |
| device pci 1c.7 off end # PCI Express Port 8 |
| device pci 1d.0 on # PCI Express Port 9 x4 SLOT 1 |
| register "PcieRpSlotImplemented[8]" = "1" |
| end |
| device pci 1d.1 off end # PCI Express Port 10 |
| device pci 1d.2 off end # PCI Express Port 11 |
| device pci 1d.3 off end # PCI Express Port 12 |
| device pci 1d.4 off end # PCI Express Port 13 |
| device pci 1d.5 off end # PCI Express Port 14 |
| device pci 1d.6 off end # PCI Express Port 15 |
| device pci 1d.7 off end # PCI Express Port 16 |
| device pci 1b.0 on # PCI Express Port 17 |
| register "PcieRpSlotImplemented[16]" = "1" |
| end |
| device pci 1b.1 on # PCI Express Port 18 |
| register "PcieRpSlotImplemented[17]" = "1" |
| end |
| device pci 1b.2 on # PCI Express Port 19 |
| register "PcieRpSlotImplemented[18]" = "1" |
| end |
| device pci 1b.3 on # PCI Express Port 20 |
| register "PcieRpSlotImplemented[19]" = "1" |
| end |
| device pci 1b.4 on # PCI Express Port 21 X4 SLOT 2 |
| register "PcieRpSlotImplemented[20]" = "1" |
| end |
| device pci 1e.1 off end # UART #1 |
| device pci 1f.6 on end # GbE |
| end |
| end |