commit 6998ee069a33ab56307c43a4108276a020fc713f
author Robert Zieba <robertzieba@google.com> Mon Sep 19 10:26:51 2022 -0600
committer Felix Held <felix-coreboot@felixheld.de> Thu Mar 09 19:41:33 2023 +0000
tree 8e88a8bb8fda6d1e51cebf20b29a25096a7935eb
parent 3db7b46804fd69cd7443e4c007248c4acff9f97a

soc/amd/cezanne: Set up SoC-specific XHCI definitions

Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI.

BRANCH=guybrush
BUG=b:186792595
TEST=builds

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67939
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/Kconfig

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 170bc49..046fd23 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -70,6 +70,7 @@
 	select SOC_AMD_COMMON_FSP_DMI_TABLES
 	select SOC_AMD_COMMON_FSP_PCI
 	select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
+	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SSE2
 	select UDK_2017_BINDING
 	select USE_DDR4