| |
| config CPU_INTEL_HASWELL |
| bool |
| |
| if CPU_INTEL_HASWELL |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select SMP |
| select SSE2 |
| select UDELAY_TSC |
| select TSC_CONSTANT_RATE |
| select SMM_TSEG |
| select SMM_MODULES |
| select RELOCATABLE_MODULES |
| select DYNAMIC_CBMEM |
| select SUPPORT_CPU_UCODE_IN_CBFS |
| #select AP_IN_SIPI_WAIT |
| select TSC_SYNC_MFENCE |
| select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| |
| config BOOTBLOCK_CPU_INIT |
| string |
| default "cpu/intel/haswell/bootblock.c" |
| |
| config SERIAL_CPU_INIT |
| bool |
| default n |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 |
| |
| config IED_REGION_SIZE |
| hex |
| default 0x400000 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x100000 |
| |
| config MICROCODE_INCLUDE_PATH |
| string |
| default "src/cpu/intel/haswell" |
| |
| config RESET_ON_INVALID_RAMSTAGE_CACHE |
| bool "Reset the system on S3 wake when ramstage cache invalid." |
| default n |
| depends on RELOCATABLE_RAMSTAGE |
| help |
| The haswell romstage code caches the loaded ramstage program |
| in SMM space. On S3 wake the romstage will copy over a fresh |
| ramstage that was cached in the SMM space. This option determines |
| the action to take when the ramstage cache is invalid. If selected |
| the system will reset otherwise the ramstage will be reloaded from |
| cbfs. |
| |
| config MONOTONIC_TIMER_MSR |
| def_bool n |
| depends on INTEL_LYNXPOINT_LP |
| select HAVE_MONOTONIC_TIMER |
| help |
| Provide a monotonic timer using the 24MHz MSR counter. |
| |
| endif |