cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates
from a CBFS file is supported, however, the name implies that microcode is
present in CBFS. This has recently caused confusion both with contributions
from Google, as well as SAGE. Rename this option to
SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is
"hey, the code we have for this CPU supports loading microcode updates from
CBFS", and prevent further confusion.
Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4482
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index dbff6e0..6a008bf 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -32,7 +32,7 @@
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
- select CPU_MICROCODE_IN_CBFS if HAVE_FSP_BIN
+ select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
select TSC_SYNC_MFENCE
config BOOTBLOCK_CPU_INIT
@@ -53,12 +53,12 @@
config CPU_MICROCODE_CBFS_LOC
hex
- depends on CPU_MICROCODE_IN_CBFS
+ depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff70000
config CPU_MICROCODE_CBFS_LEN
hex
- depends on CPU_MICROCODE_IN_CBFS
+ depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xC000 if CPU_INTEL_FSP_MODEL_306AX
default 0x2800 if CPU_INTEL_FSP_MODEL_206AX
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
index 8bd790a..309ea75 100644
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
@@ -18,7 +18,7 @@
*/
unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_CPU_MICROCODE_IN_CBFS)
+#if IS_ENABLED(SUPPORT_CPU_UCODE_IN_CBFS)
#include "microcode_blob.h"
#endif
};
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 7b6fc43..03c3518 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -14,7 +14,7 @@
select SMM_MODULES
select RELOCATABLE_MODULES
select DYNAMIC_CBMEM
- select CPU_MICROCODE_IN_CBFS
+ select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 1991ed8..a68b24d 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -30,11 +30,11 @@
#include <cpu/intel/microcode.h>
#ifdef __PRE_RAM__
-#if CONFIG_CPU_MICROCODE_IN_CBFS
+#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
#include <arch/cbfs.h>
#endif
#else
-#if CONFIG_CPU_MICROCODE_IN_CBFS
+#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
#include <cbfs.h>
#endif
#include <smp/spinlock.h>
@@ -82,7 +82,7 @@
return msr.hi;
}
-#if CONFIG_CPU_MICROCODE_IN_CBFS
+#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
@@ -192,7 +192,7 @@
#endif
}
-#else /* !CONFIG_CPU_MICROCODE_IN_CBFS */
+#else /* !CONFIG_SUPPORT_CPU_UCODE_IN_CBFS */
void intel_update_microcode(const void *microcode_updates)
{
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index b0f4e65..9040ebc 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -12,7 +12,7 @@
select TSC_CONSTANT_RATE
select SMM_TSEG
select HAVE_INIT_TIMER
- select CPU_MICROCODE_IN_CBFS
+ select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 5b3f893..426e613 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,7 +12,7 @@
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
- select CPU_MICROCODE_IN_CBFS
+ select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE