| chip soc/intel/meteorlake |
| |
| register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2 |
| register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 |
| register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1 |
| register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 |
| register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3 |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A4 |
| register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2 |
| register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A3 |
| register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth |
| |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A0 |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A1 |
| |
| register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" |
| register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" |
| register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" |
| register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" |
| |
| # Enable Display Port Configuration |
| register "ddi_ports_config" = "{ |
| [DDI_PORT_1] = DDI_ENABLE_HPD, |
| [DDI_PORT_2] = DDI_ENABLE_HPD, |
| [DDI_PORT_3] = DDI_ENABLE_HPD, |
| [DDI_PORT_4] = DDI_ENABLE_HPD, |
| }" |
| |
| # Temporary setting TCC of 105C = Tj max (110) - TCC_Offset (5) |
| register "tcc_offset" = "5" |
| |
| register "power_limits_config[MTL_P_682_482_CORE]" = "{ |
| .tdp_pl1_override = 33, |
| .tdp_pl2_override = 64, |
| .tdp_pl4 = 120, |
| }" |
| |
| register "serial_io_i2c_mode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| }" |
| |
| # Intel Common SoC Config |
| #+-------------------+---------------------------+ |
| #| Field | Value | |
| #+-------------------+---------------------------+ |
| #| I2C4 | cr50 TPM. Early init is | |
| #| | required to set up a BAR | |
| #| | for TPM communication | |
| #+-------------------+---------------------------+ |
| register "common_soc_config" = "{ |
| .i2c[4] = { |
| .early_init = 1, |
| .speed = I2C_SPEED_FAST, |
| .rise_time_ns = 600, |
| .fall_time_ns = 400, |
| .data_hold_time_ns = 50, |
| }, |
| }" |
| |
| register "psys_pmax_watts" = "180" |
| register "psys_pl2_watts" = "178" |
| |
| # As per doc 640982, Intel MTL-U 28W CPU supports FVM on GT and SA |
| # The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A |
| # For GT VR configuration |
| register "enable_fast_vmode[VR_DOMAIN_GT]" = "1" |
| register "cep_enable[VR_DOMAIN_GT]" = "1" |
| register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "216" # 54A |
| # For SA VR configuration |
| register "enable_fast_vmode[VR_DOMAIN_SA]" = "1" |
| register "cep_enable[VR_DOMAIN_SA]" = "1" |
| register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "108" # 27A |
| |
| device domain 0 on |
| device ref dtt on |
| chip drivers/intel/dptf |
| ## sensor information |
| register "options.tsr[0].desc" = ""DDR_SOC"" |
| register "options.tsr[1].desc" = ""Ambient"" |
| register "options.tsr[2].desc" = ""IMVP_SOC"" |
| register "options.tsr[3].desc" = ""NVME"" |
| |
| ## Passive Policy |
| register "policies.passive" = "{ |
| [0] = DPTF_PASSIVE(CPU, CPU, 65, 1000), |
| }" |
| |
| ## Critical Policy |
| register "policies.critical" = "{ |
| [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), |
| }" |
| |
| ## Power Limits Control |
| register "controls.power_limits" = "{ |
| .pl1 = { |
| .min_power = 28000, |
| .max_power = 28000, |
| .time_window_min = 28 * MSECS_PER_SEC, |
| .time_window_max = 32 * MSECS_PER_SEC, |
| .granularity = 200, |
| }, |
| .pl2 = { |
| .min_power = 64000, |
| .max_power = 64000, |
| .time_window_min = 28 * MSECS_PER_SEC, |
| .time_window_max = 32 * MSECS_PER_SEC, |
| .granularity = 1000, |
| } |
| }" |
| |
| device generic 0 alias dptf_policy on end |
| end |
| end |
| device ref pcie_rp5 on |
| # Enable WLAN Card PCIE 5 using clk 5 |
| register "pcie_rp[PCH_RP(5)]" = "{ |
| .clk_src = 5, |
| .clk_req = 5, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| chip drivers/wifi/generic |
| register "wake" = "GPE0_DW1_05" # GPP_E05 |
| register "add_acpi_dma_property" = "true" |
| device pci 00.0 on end |
| end |
| end #PCIE5 WLAN card |
| device ref pcie_rp7 on |
| # Enable LAN1 Card PCIE 7 using clk 2 |
| register "pcie_rp[PCH_RP(7)]" = "{ |
| .clk_src = 2, |
| .clk_req = 2, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| chip drivers/net |
| register "customized_leds" = "0x05af" |
| register "wake" = "GPE0_DW0_01" # GPP_D01 |
| register "device_index" = "1" |
| register "add_acpi_dma_property" = "true" |
| device pci 00.0 on end |
| end |
| end # PCIE7 LAN1 card |
| device ref pcie_rp10 on |
| # Enable LAN0 Card PCIE 10 using clk 8 |
| register "pcie_rp[PCH_RP(10)]" = "{ |
| .clk_src = 8, |
| .clk_req = 8, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| chip drivers/net |
| register "customized_leds" = "0x05af" |
| register "wake" = "GPE0_DW1_04" # GPP_E04 |
| register "device_index" = "0" |
| register "add_acpi_dma_property" = "true" |
| device pci 00.0 on end |
| end |
| end # PCIE10 LAN0 card |
| device ref pcie_rp11 on |
| # Enable SSD Card PCIE 11 using clk 7 |
| register "pcie_rp[PCH_RP(11)]" = "{ |
| .clk_src = 7, |
| .clk_req = 7, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| end # PCIE11 SSD card |
| device ref tbt_pcie_rp0 on end |
| device ref tbt_pcie_rp1 on end |
| device ref tbt_pcie_rp2 on end |
| device ref tbt_pcie_rp3 on end |
| device ref tcss_xhci on |
| chip drivers/usb/acpi |
| device ref tcss_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C Port C0"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" |
| device ref tcss_usb3_port0 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C Port C1"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" |
| device ref tcss_usb3_port2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C Port C2"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))" |
| device ref tcss_usb3_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C Port C3"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))" |
| device ref tcss_usb3_port3 on end |
| end |
| end |
| end |
| end |
| device ref tcss_dma0 on |
| chip drivers/intel/usb4/retimer |
| register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" |
| use tcss_usb3_port0 as dfp[0].typec_port |
| device generic 0 on end |
| end |
| chip drivers/intel/usb4/retimer |
| register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" |
| use tcss_usb3_port1 as dfp[1].typec_port |
| device generic 0 on end |
| end |
| end |
| device ref tcss_dma1 on |
| chip drivers/intel/usb4/retimer |
| register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" |
| use tcss_usb3_port2 as dfp[0].typec_port |
| device generic 0 on end |
| end |
| chip drivers/intel/usb4/retimer |
| register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" |
| use tcss_usb3_port3 as dfp[1].typec_port |
| device generic 0 on end |
| end |
| end |
| device ref xhci on |
| chip drivers/usb/acpi |
| device ref xhci_root_hub on |
| # FIXME - location need to be corrected once we have the final design |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C Port C0"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" |
| device ref usb2_port2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C Port C1"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" |
| device ref usb2_port3 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C Port C2"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))" |
| device ref usb2_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C Port C3"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))" |
| device ref usb2_port5 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port A0"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" |
| device ref usb2_port4 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port A1"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" |
| device ref usb2_port7 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port A2"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 3))" |
| device ref usb2_port8 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port A3"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))" |
| device ref usb2_port9 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port A4"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(5, 5))" |
| device ref usb2_port6 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" |
| device ref usb2_port10 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Port A0"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" |
| device ref usb3_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Port A1"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" |
| device ref usb3_port2 on end |
| end |
| end |
| end |
| end |
| device ref cnvi_wifi on |
| chip drivers/wifi/generic |
| register "wake" = "GPE0_PME_B0" |
| register "add_acpi_dma_property" = "true" |
| register "enable_cnvi_ddr_rfim" = "true" |
| device generic 0 on end |
| end |
| end |
| device ref i2c4 on |
| chip drivers/i2c/tpm |
| register "hid" = ""GOOG0005"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)" |
| device i2c 50 on end |
| end |
| end |
| device ref soc_espi on |
| chip ec/google/chromeec |
| use conn0 as mux_conn[0] |
| use conn1 as mux_conn[1] |
| use conn2 as mux_conn[2] |
| use conn3 as mux_conn[3] |
| device pnp 0c09.0 on end |
| end |
| end |
| device ref pmc hidden |
| chip drivers/intel/pmc_mux |
| device generic 0 on |
| chip drivers/intel/pmc_mux/conn |
| #USB2_C0 |
| use usb2_port2 as usb2_port |
| use tcss_usb3_port0 as usb3_port |
| device generic 0 alias conn0 on end |
| end |
| chip drivers/intel/pmc_mux/conn |
| #USB2_C1 |
| use usb2_port3 as usb2_port |
| use tcss_usb3_port2 as usb3_port |
| device generic 1 alias conn1 on end |
| end |
| chip drivers/intel/pmc_mux/conn |
| #USB2_C2 |
| use usb2_port1 as usb2_port |
| use tcss_usb3_port1 as usb3_port |
| device generic 2 alias conn2 on end |
| end |
| chip drivers/intel/pmc_mux/conn |
| #USB2_C3 |
| use usb2_port5 as usb2_port |
| use tcss_usb3_port3 as usb3_port |
| device generic 3 alias conn3 on end |
| end |
| end |
| end |
| end |
| end |
| end |