broadwell: ACPI, romstage, and other updates
broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)
broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)
broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)
broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)
broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)
broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)
broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)
broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)
broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)
broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)
broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)
broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)
broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)
broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)
broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)
Squashed 15 commits for broadwell support.
Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index 9ac8331..82390a4 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -92,91 +92,88 @@
void pch_disable_devfn(device_t dev)
{
switch (dev->path.pci.devfn) {
- case PCI_DEVFN(19, 0): /* Audio DSP */
+ case PCH_DEVFN_ADSP: /* Audio DSP */
RCBA32_OR(FD, PCH_DISABLE_ADSPD);
break;
- case PCI_DEVFN(20, 0): /* XHCI */
+ case PCH_DEVFN_XHCI: /* XHCI */
RCBA32_OR(FD, PCH_DISABLE_XHCI);
break;
- case PCI_DEVFN(21, 0): /* DMA */
+ case PCH_DEVFN_SDMA: /* DMA */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(21, 1): /* I2C0 */
+ case PCH_DEVFN_I2C0: /* I2C0 */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(21, 2): /* I2C1 */
+ case PCH_DEVFN_I2C1: /* I2C1 */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(21, 3): /* SPI0 */
+ case PCH_DEVFN_SPI0: /* SPI0 */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(21, 4): /* SPI1 */
+ case PCH_DEVFN_SPI1: /* SPI1 */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(21, 5): /* UART0 */
+ case PCH_DEVFN_UART0: /* UART0 */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(21, 6): /* UART1 */
+ case PCH_DEVFN_UART1: /* UART1 */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(22, 0): /* MEI #1 */
+ case PCH_DEVFN_ME: /* MEI #1 */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
break;
- case PCI_DEVFN(22, 1): /* MEI #2 */
+ case PCH_DEVFN_ME_2: /* MEI #2 */
RCBA32_OR(FD2, PCH_DISABLE_MEI2);
break;
- case PCI_DEVFN(22, 2): /* IDE-R */
+ case PCH_DEVFN_ME_IDER: /* IDE-R */
RCBA32_OR(FD2, PCH_DISABLE_IDER);
break;
- case PCI_DEVFN(22, 3): /* KT */
+ case PCH_DEVFN_ME_KT: /* KT */
RCBA32_OR(FD2, PCH_DISABLE_KT);
break;
- case PCI_DEVFN(23, 0): /* SDIO */
+ case PCH_DEVFN_SDIO: /* SDIO */
pch_enable_d3hot(dev);
pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
break;
- case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
+ case PCH_DEVFN_GBE: /* Gigabit Ethernet */
RCBA32_OR(BUC, PCH_DISABLE_GBE);
break;
- case PCI_DEVFN(26, 0): /* EHCI #2 */
- RCBA32_OR(FD, PCH_DISABLE_EHCI2);
- break;
- case PCI_DEVFN(27, 0): /* HD Audio Controller */
+ case PCH_DEVFN_HDA: /* HD Audio Controller */
RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
break;
- case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
- case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
- case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
- case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
- case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
- case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
- case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
- case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 0): /* PCI Express Root Port 1 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 1): /* PCI Express Root Port 2 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 2): /* PCI Express Root Port 3 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 3): /* PCI Express Root Port 4 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 4): /* PCI Express Root Port 5 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 5): /* PCI Express Root Port 6 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 6): /* PCI Express Root Port 7 */
+ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 7): /* PCI Express Root Port 8 */
RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
break;
- case PCI_DEVFN(29, 0): /* EHCI #1 */
+ case PCH_DEVFN_EHCI: /* EHCI #1 */
RCBA32_OR(FD, PCH_DISABLE_EHCI1);
break;
- case PCI_DEVFN(31, 0): /* LPC */
+ case PCH_DEVFN_LPC: /* LPC */
RCBA32_OR(FD, PCH_DISABLE_LPC);
break;
- case PCI_DEVFN(31, 2): /* SATA #1 */
+ case PCH_DEVFN_SATA: /* SATA #1 */
RCBA32_OR(FD, PCH_DISABLE_SATA1);
break;
- case PCI_DEVFN(31, 3): /* SMBUS */
+ case PCH_DEVFN_SMBUS: /* SMBUS */
RCBA32_OR(FD, PCH_DISABLE_SMBUS);
break;
- case PCI_DEVFN(31, 5): /* SATA #2 */
+ case PCH_DEVFN_SATA2: /* SATA #2 */
RCBA32_OR(FD, PCH_DISABLE_SATA2);
break;
- case PCI_DEVFN(31, 6): /* Thermal Subsystem */
+ case PCH_DEVFN_THERMAL: /* Thermal Subsystem */
RCBA32_OR(FD, PCH_DISABLE_THERMAL);
break;
}
@@ -186,9 +183,13 @@
{
u32 reg32;
- /* PCH PCIe Root Ports are handled in PCIe driver. */
- if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_PCIE)
+ /* These devices need special enable/disable handling */
+ switch (PCI_SLOT(dev->path.pci.devfn)) {
+ case PCH_DEV_SLOT_PCIE:
+ case PCH_DEV_SLOT_EHCI:
+ case PCH_DEV_SLOT_HDA:
return;
+ }
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));