Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <broadwell/iobp.h> |
| 28 | #include <broadwell/pch.h> |
| 29 | #include <broadwell/pci_devs.h> |
| 30 | #include <broadwell/ramstage.h> |
| 31 | #include <broadwell/rcba.h> |
| 32 | #include <broadwell/serialio.h> |
| 33 | #include <broadwell/spi.h> |
| 34 | |
| 35 | u8 pch_revision(void) |
| 36 | { |
| 37 | return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID); |
| 38 | } |
| 39 | |
| 40 | u16 pch_type(void) |
| 41 | { |
| 42 | return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); |
| 43 | } |
| 44 | |
| 45 | /* Return 1 if PCH type is WildcatPoint */ |
| 46 | int pch_is_wpt(void) |
| 47 | { |
| 48 | return ((pch_type() & 0xfff0) == 0x9cc0) ? 1 : 0; |
| 49 | } |
| 50 | |
| 51 | /* Return 1 if PCH type is WildcatPoint ULX */ |
| 52 | int pch_is_wpt_ulx(void) |
| 53 | { |
| 54 | u16 lpcid = pch_type(); |
| 55 | |
| 56 | switch (lpcid) { |
| 57 | case PCH_WPT_BDW_Y_SAMPLE: |
| 58 | case PCH_WPT_BDW_Y_PREMIUM: |
| 59 | case PCH_WPT_BDW_Y_BASE: |
| 60 | return 1; |
| 61 | } |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | u32 pch_read_soft_strap(int id) |
| 67 | { |
| 68 | u32 fdoc; |
| 69 | |
| 70 | fdoc = SPIBAR32(SPIBAR_FDOC); |
| 71 | fdoc &= ~0x00007ffc; |
| 72 | SPIBAR32(SPIBAR_FDOC) = fdoc; |
| 73 | |
| 74 | fdoc |= 0x00004000; |
| 75 | fdoc |= id * 4; |
| 76 | SPIBAR32(SPIBAR_FDOC) = fdoc; |
| 77 | |
| 78 | return SPIBAR32(SPIBAR_FDOD); |
| 79 | } |
| 80 | |
| 81 | #ifndef __PRE_RAM__ |
| 82 | |
| 83 | /* Put device in D3Hot Power State */ |
| 84 | static void pch_enable_d3hot(device_t dev) |
| 85 | { |
| 86 | u32 reg32 = pci_read_config32(dev, PCH_PCS); |
| 87 | reg32 |= PCH_PCS_PS_D3HOT; |
| 88 | pci_write_config32(dev, PCH_PCS, reg32); |
| 89 | } |
| 90 | |
| 91 | /* Set bit in Function Disble register to hide this device */ |
| 92 | void pch_disable_devfn(device_t dev) |
| 93 | { |
| 94 | switch (dev->path.pci.devfn) { |
| 95 | case PCI_DEVFN(19, 0): /* Audio DSP */ |
| 96 | RCBA32_OR(FD, PCH_DISABLE_ADSPD); |
| 97 | break; |
| 98 | case PCI_DEVFN(20, 0): /* XHCI */ |
| 99 | RCBA32_OR(FD, PCH_DISABLE_XHCI); |
| 100 | break; |
| 101 | case PCI_DEVFN(21, 0): /* DMA */ |
| 102 | pch_enable_d3hot(dev); |
| 103 | pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 104 | break; |
| 105 | case PCI_DEVFN(21, 1): /* I2C0 */ |
| 106 | pch_enable_d3hot(dev); |
| 107 | pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 108 | break; |
| 109 | case PCI_DEVFN(21, 2): /* I2C1 */ |
| 110 | pch_enable_d3hot(dev); |
| 111 | pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 112 | break; |
| 113 | case PCI_DEVFN(21, 3): /* SPI0 */ |
| 114 | pch_enable_d3hot(dev); |
| 115 | pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 116 | break; |
| 117 | case PCI_DEVFN(21, 4): /* SPI1 */ |
| 118 | pch_enable_d3hot(dev); |
| 119 | pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 120 | break; |
| 121 | case PCI_DEVFN(21, 5): /* UART0 */ |
| 122 | pch_enable_d3hot(dev); |
| 123 | pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 124 | break; |
| 125 | case PCI_DEVFN(21, 6): /* UART1 */ |
| 126 | pch_enable_d3hot(dev); |
| 127 | pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 128 | break; |
| 129 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 130 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 131 | break; |
| 132 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 133 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 134 | break; |
| 135 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 136 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 137 | break; |
| 138 | case PCI_DEVFN(22, 3): /* KT */ |
| 139 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 140 | break; |
| 141 | case PCI_DEVFN(23, 0): /* SDIO */ |
| 142 | pch_enable_d3hot(dev); |
| 143 | pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 144 | break; |
| 145 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 146 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 147 | break; |
| 148 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 149 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 150 | break; |
| 151 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 152 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 153 | break; |
| 154 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 155 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 156 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 157 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 158 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 159 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 160 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 161 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 162 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); |
| 163 | break; |
| 164 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 165 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 166 | break; |
| 167 | case PCI_DEVFN(31, 0): /* LPC */ |
| 168 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 169 | break; |
| 170 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 171 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 172 | break; |
| 173 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 174 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 175 | break; |
| 176 | case PCI_DEVFN(31, 5): /* SATA #2 */ |
| 177 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 178 | break; |
| 179 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 180 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 181 | break; |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | void broadwell_pch_enable_dev(device_t dev) |
| 186 | { |
| 187 | u32 reg32; |
| 188 | |
| 189 | /* PCH PCIe Root Ports are handled in PCIe driver. */ |
| 190 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_PCIE) |
| 191 | return; |
| 192 | |
| 193 | if (!dev->enabled) { |
| 194 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 195 | |
| 196 | /* Ensure memory, io, and bus master are all disabled */ |
| 197 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 198 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 199 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 200 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 201 | |
| 202 | /* Disable this device if possible */ |
| 203 | pch_disable_devfn(dev); |
| 204 | } else { |
| 205 | /* Enable SERR */ |
| 206 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 207 | reg32 |= PCI_COMMAND_SERR; |
| 208 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | #endif |