| # SPDX-License-Identifier: GPL-2.0-or-later |
| |
| source "src/soc/intel/xeon_sp/skx/Kconfig" |
| source "src/soc/intel/xeon_sp/cpx/Kconfig" |
| source "src/soc/intel/xeon_sp/ras/Kconfig" |
| |
| config XEON_SP_COMMON_BASE |
| bool |
| |
| config SOC_INTEL_SKYLAKE_SP |
| bool |
| select XEON_SP_COMMON_BASE |
| select PLATFORM_USES_FSP2_0 |
| select NO_FSP_TEMP_RAM_EXIT |
| help |
| Intel Skylake-SP support |
| |
| config SOC_INTEL_COOPERLAKE_SP |
| bool |
| select XEON_SP_COMMON_BASE |
| select PLATFORM_USES_FSP2_2 |
| select CACHE_MRC_SETTINGS |
| select NO_FSP_TEMP_RAM_EXIT |
| help |
| Intel Cooper Lake-SP support |
| |
| if XEON_SP_COMMON_BASE |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| select ARCH_X86 |
| select BOOT_DEVICE_SUPPORTS_WRITES |
| select CPU_INTEL_COMMON |
| select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| select FSP_CAR |
| select FSP_M_XIP |
| select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
| select FSP_T_XIP |
| select HAVE_SMI_HANDLER |
| select INTEL_CAR_NEM # For postcar only now |
| select INTEL_DESCRIPTOR_MODE_CAPABLE |
| select PARALLEL_MP_AP_WORK |
| select PMC_GLOBAL_RESET_ENABLE_LOCK |
| select POSTCAR_STAGE |
| select REG_SCRIPT |
| select SMM_TSEG |
| select SOC_INTEL_COMMON |
| select SOC_INTEL_COMMON_RESET |
| select SOC_INTEL_COMMON_BLOCK |
| select SOC_INTEL_COMMON_BLOCK_ACPI |
| select SOC_INTEL_COMMON_BLOCK_CPU |
| select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
| select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE |
| select SOC_INTEL_COMMON_BLOCK_SMM |
| select SOC_INTEL_COMMON_BLOCK_TCO |
| select SOC_INTEL_COMMON_PCH_SERVER |
| select SUPPORT_CPU_UCODE_IN_CBFS |
| select TSC_MONOTONIC_TIMER |
| select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT |
| select UDELAY_TSC |
| select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
| |
| config MAINBOARD_USES_FSP2_0 |
| bool |
| default y |
| |
| config USE_FSP2_0_DRIVER |
| def_bool y |
| depends on MAINBOARD_USES_FSP2_0 |
| select PLATFORM_USES_FSP2_0 |
| select UDK_202005_BINDING |
| select POSTCAR_STAGE |
| |
| config MAX_SOCKET |
| int |
| default 2 |
| |
| config MAX_HECI_DEVICES |
| int |
| default 5 |
| |
| # For 2S config, the number of cpus could be as high as |
| # 2 threads * 20 cores * 2 sockets |
| config MAX_CPUS |
| int |
| default 80 |
| |
| config INTEL_ACPI_BASE_ADDRESS |
| hex |
| default 0x500 |
| help |
| IO Address of ACPI. |
| |
| config INTEL_PCH_PWRM_BASE_ADDRESS |
| hex |
| default 0xfe000000 |
| help |
| PCH PWRM Base address. |
| |
| config PCR_BASE_ADDRESS |
| hex |
| default 0xfd000000 |
| help |
| This option allows you to select MMIO Base Address of sideband bus. |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x10000 |
| |
| config ECAM_MMCONF_BASE_ADDRESS |
| default 0x80000000 |
| |
| config ECAM_MMCONF_BUS_NUMBER |
| default 256 |
| |
| config HEAP_SIZE |
| hex |
| default 0x80000 |
| |
| config HPET_MIN_TICKS |
| hex |
| default 0x80 |
| |
| config SOC_INTEL_XEON_RAS |
| bool |
| select SOC_ACPI_HEST |
| select SOC_RAS_ELOG |
| |
| endif ## SOC_INTEL_XEON_SP |