| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2010 Google Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config NORTHBRIDGE_INTEL_HASWELL |
| bool |
| select CPU_INTEL_HASWELL |
| select CACHE_MRC_SETTINGS |
| select INTEL_DDI |
| select INTEL_GMA_ACPI |
| select BOOTBLOCK_CONSOLE |
| |
| if NORTHBRIDGE_INTEL_HASWELL |
| |
| config HASWELL_VBOOT_IN_BOOTBLOCK |
| depends on VBOOT |
| bool "Start verstage in bootblock" |
| default y |
| select VBOOT_STARTS_IN_BOOTBLOCK |
| select VBOOT_SEPARATE_VERSTAGE |
| help |
| Haswell can either start verstage in a separate stage |
| right after the bootblock has run or it can start it |
| after romstage for compatibility reasons. |
| Haswell however uses a mrc.bin to initialize memory which |
| needs to be located at a fixed offset. Therefore even with |
| a separate verstage starting after the bootblock that same |
| binary is used meaning a jump is made from RW to the RO region |
| and back to the RW region after the binary is done. |
| |
| config VBOOT |
| select VBOOT_MUST_REQUEST_DISPLAY |
| select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK |
| |
| config VGA_BIOS_ID |
| string |
| default "8086,0166" |
| |
| config MMCONF_BASE_ADDRESS |
| hex |
| default 0xf0000000 |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xff7c0000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x10000 |
| help |
| The size of the cache-as-ram region required during bootblock |
| and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| must add up to a power of 2. |
| |
| config DCACHE_RAM_MRC_VAR_SIZE |
| hex |
| default 0x30000 |
| help |
| The amount of cache-as-ram region required by the reference code. |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x2000 |
| help |
| The amount of anticipated stack usage in CAR by bootblock and |
| other stages. |
| |
| config HAVE_MRC |
| bool "Add a System Agent binary" |
| help |
| Select this option to add a System Agent binary to |
| the resulting coreboot image. |
| |
| Note: Without this binary coreboot will not work |
| |
| config MRC_FILE |
| string "Intel System Agent path and filename" |
| depends on HAVE_MRC |
| default "mrc.bin" |
| help |
| The path and filename of the file to use as System Agent |
| binary. |
| |
| config PRE_GRAPHICS_DELAY |
| int "Graphics initialization delay in ms" |
| default 0 |
| help |
| On some systems, coreboot boots so fast that connected monitors |
| (mostly TVs) won't be able to wake up fast enough to talk to the |
| VBIOS. On those systems we need to wait for a bit before executing |
| the VBIOS. |
| |
| # The UEFI System Agent binary needs to be at a fixed offset in the flash |
| # and can therefore only reside in the COREBOOT fmap region |
| config RO_REGION_ONLY |
| string |
| depends on VBOOT |
| default "mrc.bin" |
| |
| endif |