| # TODO These two options look too similar |
| config PARALLEL_CPU_INIT |
| bool |
| default n |
| |
| config PARALLEL_MP |
| def_bool n |
| help |
| This option uses common MP infrastructure for bringing up APs |
| in parallel. It additionally provides a more flexible mechanism |
| for sequencing the steps of bringing up the APs. |
| |
| config PARALLEL_MP_AP_WORK |
| def_bool n |
| depends on PARALLEL_MP |
| help |
| Allow APs to do other work after initialization instead of going |
| to sleep. |
| |
| config UDELAY_LAPIC |
| bool |
| default n |
| |
| config LAPIC_MONOTONIC_TIMER |
| def_bool n |
| depends on UDELAY_LAPIC |
| help |
| Expose monotonic time using the local APIC. |
| |
| config UDELAY_LAPIC_FIXED_FSB |
| int |
| |
| config UDELAY_TSC |
| bool |
| default n |
| |
| config UNKNOWN_TSC_RATE |
| bool |
| default y if LAPIC_MONOTONIC_TIMER |
| |
| config TSC_MONOTONIC_TIMER |
| def_bool n |
| depends on UDELAY_TSC |
| help |
| Expose monotonic time using the TSC. |
| |
| config TSC_SYNC_LFENCE |
| bool |
| default n |
| help |
| The CPU driver should select this if the CPU needs |
| to execute an lfence instruction in order to synchronize |
| rdtsc. This is true for all modern AMD CPUs. |
| |
| config TSC_SYNC_MFENCE |
| bool |
| default n |
| help |
| The CPU driver should select this if the CPU needs |
| to execute an mfence instruction in order to synchronize |
| rdtsc. This is true for all modern Intel CPUs. |
| |
| config NO_FIXED_XIP_ROM_SIZE |
| bool |
| default n |
| help |
| The XIP_ROM_SIZE Kconfig variable is used globally on x86 |
| with the assumption that all chipsets utilize this value. |
| For the chipsets which do not use the variable it can lead |
| to unnecessary alignment constraints in cbfs for romstage. |
| Therefore, allow those chipsets a path to not be burdened. |
| |
| config XIP_ROM_SIZE |
| hex |
| depends on !NO_FIXED_XIP_ROM_SIZE |
| default 0x10000 |
| |
| config SETUP_XIP_CACHE |
| bool |
| depends on !NO_XIP_EARLY_STAGES |
| help |
| Select this option to set up an MTRR to cache XIP stages loaded |
| from the bootblock. This is useful on platforms lacking a |
| non-eviction mode and therefore need to be careful to avoid |
| eviction. |
| |
| config CPU_ADDR_BITS |
| int |
| default 36 |
| |
| config LOGICAL_CPUS |
| bool |
| default y |
| |
| config HAVE_SMI_HANDLER |
| bool |
| default n |
| depends on (SMM_ASEG || SMM_TSEG) |
| |
| config NO_SMM |
| bool |
| default n |
| |
| config SMM_ASEG |
| bool |
| default n |
| depends on !NO_SMM |
| |
| config SMM_TSEG |
| bool |
| default y |
| depends on !(NO_SMM || SMM_ASEG) |
| |
| if SMM_TSEG |
| |
| config SMM_MODULE_HEAP_SIZE |
| hex |
| default 0x4000 |
| help |
| This option determines the size of the heap within the SMM handler |
| modules. |
| |
| config SMM_MODULE_STACK_SIZE |
| hex |
| default 0x400 |
| help |
| This option determines the size of the stack within the SMM handler |
| modules. |
| |
| config SMM_STUB_STACK_SIZE |
| hex |
| default 0x400 |
| help |
| This option determines the size of the stack within the SMM handler |
| modules. |
| |
| endif |
| |
| config SMM_LAPIC_REMAP_MITIGATION |
| bool |
| default y if NORTHBRIDGE_INTEL_I945 |
| default y if NORTHBRIDGE_INTEL_GM45 |
| default y if NORTHBRIDGE_INTEL_IRONLAKE |
| default n |
| |
| config SERIALIZED_SMM_INITIALIZATION |
| bool |
| default n |
| help |
| On some CPUs, there is a race condition in SMM. |
| This can occur when both hyperthreads change SMM state |
| variables in parallel without coordination. |
| Setting this option serializes the SMM initialization |
| to avoid an ugly hang in the boot process at the cost |
| of a slightly longer boot time. |
| |
| config X86_AMD_FIXED_MTRRS |
| bool |
| default n |
| help |
| This option informs the MTRR code to use the RdMem and WrMem fields |
| in the fixed MTRR MSRs. |
| |
| config X86_AMD_INIT_SIPI |
| bool |
| default n |
| help |
| This option limits the number of SIPI signals sent during during the |
| common AP setup. Intel documentation specifies an INIT SIPI SIPI |
| sequence, however this doesn't work on some AMD platforms. |
| |
| config SOC_SETS_MSRS |
| bool |
| default n |
| help |
| The SoC requires different access methods for reading and writing |
| the MSRs. Use SoC specific routines to handle the MSR access. |