southbrige/intel/bd82x6x: add XHCI overcurrent map config
Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9449
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index f4be82d..f14f4ad 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -94,6 +94,8 @@
uint32_t xhci_switchable_ports;
/* Ports which support SuperSpeed (USB 3.0 additional lanes). */
uint32_t superspeed_capable_ports;
+ /* Overcurrent Mapping for USB 3.0 Ports */
+ uint32_t xhci_overcurrent_mapping;
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7b52ebc..4ec2903 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -449,6 +449,7 @@
#define USBOCM2 0x35a4 /* 32bit */
/* XHCI USB 3.0 */
+#define XOCM 0xc0 /* 32bit */
#define XUSB2PRM 0xd4 /* 32bit */
#define USB3PRM 0xdc /* 32bit */
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 3e6ce6b..639d640 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -33,6 +33,9 @@
printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
+ if (config->xhci_overcurrent_mapping)
+ pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
+
/* lock overcurrent map */
reg32 = pci_read_config32(dev, 0x44);
reg32 |= 1;