Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
598c0dda158bd2062442cbf0b42214d5ed95006f
/
.
/
src
/
soc
/
intel
/
common
/
block
/
scs
/
Makefile.inc
blob: 0b77f5fa2184c621f11c1116e6d1daf52771d5c8 [
file
] [
log
] [
blame
]
ifneq
(
$
(
CONFIG_SOC_INTEL_ALDERLAKE_PCH_N
),
y
)
ramstage
-
$
(
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS
)
+=
sd
.
c
endif
ramstage
-
$
(
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS
)
+=
mmc
.
c
romstage
-
$
(
CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE
)
+=
early_mmc
.
c