| # |
| # This file is part of the coreboot project. |
| # |
| # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| # |
| # This program is free software; you can redistribute it and/or modify |
| # it under the terms of the GNU General Public License as published by |
| # the Free Software Foundation; version 2 of the License. |
| # |
| # This program is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| # GNU General Public License for more details. |
| # |
| # You should have received a copy of the GNU General Public License |
| # along with this program; if not, write to the Free Software |
| # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| # |
| |
| config CPU_AMD_AGESA |
| bool |
| default y if CPU_AMD_AGESA_FAMILY10 |
| default y if CPU_AMD_AGESA_FAMILY12 |
| default y if CPU_AMD_AGESA_FAMILY14 |
| default y if CPU_AMD_AGESA_FAMILY15 |
| default y if CPU_AMD_AGESA_FAMILY15_TN |
| default y if CPU_AMD_AGESA_FAMILY16_KB |
| default y if CPU_AMD_AGESA_00730F01 |
| default n |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select TSC_SYNC_LFENCE |
| select UDELAY_LAPIC |
| select LAPIC_MONOTONIC_TIMER |
| select BROKEN_CAR_MIGRATE |
| select SPI_FLASH if HAVE_ACPI_RESUME |
| |
| if CPU_AMD_AGESA |
| |
| config UDELAY_IO |
| bool |
| default n |
| |
| config XIP_ROM_SIZE |
| hex |
| default 0x100000 |
| help |
| Overwride the default write through caching size as 1M Bytes. |
| On some AMD platforms, one socket supports 2 or more kinds of |
| processor family, compiling several CPU families agesa code |
| will increase the romstage size. |
| In order to execute romstage in place on the flash ROM, |
| more space is required to be set as write through caching. |
| |
| config UDELAY_LAPIC_FIXED_FSB |
| int |
| default 200 |
| |
| # TODO: Sync these with definitions in AGESA vendorcode. |
| # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0x30000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x10000 |
| |
| config S3_DATA_POS |
| hex |
| default 0xFFFF0000 |
| |
| config S3_DATA_SIZE |
| int |
| default 32768 |
| |
| endif # CPU_AMD_AGESA |
| |
| source src/cpu/amd/agesa/family10/Kconfig |
| source src/cpu/amd/agesa/family12/Kconfig |
| source src/cpu/amd/agesa/family14/Kconfig |
| source src/cpu/amd/agesa/family15/Kconfig |
| source src/cpu/amd/agesa/family15tn/Kconfig |
| source src/cpu/amd/agesa/family16kb/Kconfig |
| source src/cpu/amd/agesa/00730F01/Kconfig |
| |