src/mainboard/intel/saddlebrook/devicetree.cb

## SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/skylake

	register "deep_s5_enable_ac" = "0"
	register "deep_s5_enable_dc" = "0"
	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	# FSP Configuration
	register "DspEnable" = "1"
	register "IoBufferOwnership" = "3"
	register "SkipExtGfxScan" = "1"

	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
	register "PmConfigSlpS3MinAssert" = "0x02"

	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
	register "PmConfigSlpS4MinAssert" = "0x04"

	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
	register "PmConfigSlpSusMinAssert" = "0x03"

	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
	register "PmConfigSlpAMinAssert" = "0x03"

	# VR Settings Configuration for 4 Domains
	#+----------------+-----------+-----------+-------------+----------+
	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
	#+----------------+-----------+-----------+-------------+----------+
	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
	#| Psi3Enable     | 1         | 1         | 1           | 1        |
	#| Psi4Enable     | 1         | 1         | 1           | 1        |
	#| ImonSlope      | 0         | 0         | 0           | 0        |
	#| ImonOffset     | 0         | 0         | 0           | 0        |
	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
	#+----------------+-----------+-----------+-------------+----------+
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(4),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(7),
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(34),
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(35),
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(35),
		.voltage_limit = 1520,
	}"

	# Enable x1 slot
	register "PcieRpEnable[7]" = "1"
	register "PcieRpClkReqSupport[7]" = "1"
	register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3

	# Enable x4 slot
	register "PcieRpEnable[8]" = "1"
	register "PcieRpClkReqSupport[8]" = "1"
	register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4

	# Enable Root port 6 and 13.
	register "PcieRpEnable[5]" = "1"
	register "PcieRpEnable[12]" = "1"

	# Enable CLKREQ#
	register "PcieRpClkReqSupport[5]" = "1"
	register "PcieRpClkReqSupport[12]" = "1"

	# RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#
	register "PcieRpClkReqNumber[5]" = "0"
	register "PcieRpClkReqNumber[12]" = "1"

	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V

	# Must leave UART0 enabled or SD/eMMC will not work as PCI

	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]	= PchSerialIoPci,
		[PchSerialIoIndexI2C1]	= PchSerialIoPci,
		[PchSerialIoIndexI2C2]	= PchSerialIoPci,
		[PchSerialIoIndexI2C3]	= PchSerialIoPci,
		[PchSerialIoIndexI2C4]	= PchSerialIoPci,
		[PchSerialIoIndexI2C5]	= PchSerialIoPci,
		[PchSerialIoIndexSpi0]	= PchSerialIoPci,
		[PchSerialIoIndexSpi1]	= PchSerialIoPci,
		[PchSerialIoIndexUart0]	= PchSerialIoPci,
		[PchSerialIoIndexUart1]	= PchSerialIoPci,
		[PchSerialIoIndexUart2]	= PchSerialIoSkipInit,
	}"

	# PL2 override 25W
	register "power_limits_config" = "{
		.tdp_pl2_override = 25,
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	# Use default SD card detect GPIO configuration
	#register "sdcard_cd_gpio" = "GPP_A7"

	device domain 0 on
		device ref igpu		on end
		device ref south_xhci	on
			register "SsicPortEnable" = "1"

			register "usb2_ports" = "{
				[0] = USB2_PORT_MID(OC_SKIP),	/* OTG */
				[1] = USB2_PORT_MID(OC3),	/* Touch Pad */
				[2] = USB2_PORT_MID(OC_SKIP),	/* M.2 BT */
				[3] = USB2_PORT_MID(OC_SKIP),	/* Touch Panel */
				[4] = USB2_PORT_MID(OC_SKIP),	/* M.2 WWAN */
				[5] = USB2_PORT_MID(OC0),	/* Front Panel */
				[6] = USB2_PORT_MID(OC0),	/* Front Panel */
				[7] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
				[8] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
				[9] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
				[10] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
				[11] = USB2_PORT_MID(OC_SKIP),	/* Finger print sensor */
				[12] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
				[13] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
			}"

			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC5),		/* OTG */
				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* M.2 WWAN */
				[2] = USB3_PORT_DEFAULT(OC3),		/* Flex */
				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* IVCAM */
				[4] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
				[5] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
				[6] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
				[7] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
				[8] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
				[9] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
			}"
		end
		device ref thermal	on end
		device ref i2c0		on end
		device ref i2c1		on end
		device ref i2c2		on end
		device ref i2c3		on end
		device ref heci1	on end
		device ref sata		on
			register "SataSalpSupport" = "1"
			register "SataPortsEnable" = "{
				[0] = 1,
				[1] = 1,
				[2] = 1,
				[3] = 1,
				[4] = 1,
				[5] = 1,
				[6] = 1,
				[7] = 1,
			}"
		end
		device ref uart2	on end
		device ref i2c5		on end
		device ref i2c4		on end
		device ref pcie_rp1	on end
		device ref uart0	on end
		device ref uart1	on end
		device ref gspi0	on end
		device ref gspi1	on end
		device ref hda		on end
		device ref smbus	on end
		device ref lpc_espi	on
			register "serirq_mode" = "SERIRQ_CONTINUOUS"
		end
		device ref fast_spi	on end
		device ref gbe		on end
	end
end