skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope
Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index 8a3161a..9d4c0d9 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -41,10 +41,6 @@
# RP17, uses CLK SRC 7
register "PcieRpClkSrcNumber[16]" = "7"
- # USB related
- register "SsicPortEnable" = "1"
-
-
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
@@ -66,6 +62,8 @@
device domain 0 on
device ref south_xhci on
+ register "SsicPortEnable" = "1"
+
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 0af8282..7de1454 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -71,9 +71,6 @@
# RP10, uses CLK SRC 4
register "PcieRpClkSrcNumber[9]" = "4"
-
- register "SsicPortEnable" = "1" # Enable SSIC for WWAN
-
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -91,6 +88,8 @@
device domain 0 on
device ref south_xhci on
+ register "SsicPortEnable" = "1" # Enable SSIC for WWAN
+
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 010312c..eb13212 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -93,9 +93,6 @@
register "PcieRpClkReqNumber[8]" = "6"
register "PcieRpClkReqNumber[16]" = "7"
-
- register "SsicPortEnable" = "1" # Enable SSIC for WWAN
-
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -118,6 +115,8 @@
device domain 0 on
device ref south_xhci on
+ register "SsicPortEnable" = "1" # Enable SSIC for WWAN
+
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC2), /* Type-C Port */
[1] = USB2_PORT_MAX(OC5), /* Front panel */
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 2f5058d..c92377a 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -120,10 +120,6 @@
register "PcieRpClkReqNumber[5]" = "0"
register "PcieRpClkReqNumber[12]" = "1"
- # USB related
- register "SsicPortEnable" = "1"
-
-
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
@@ -156,6 +152,8 @@
device domain 0 on
device ref igpu on end
device ref south_xhci on
+ register "SsicPortEnable" = "1"
+
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */