| #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) |
| #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) |
| #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, |
| # 1: the system allows a PCIE link to be established on Dev2 or Dev3. |
| #Define gfx_dual_slot, 0: single slot, 1: dual slot |
| #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable |
| #Define gfx_tmds, 0: didn't support TMDS, 1: support |
| #Define gfx_compliance, 0: didn't support compliance, 1: support |
| #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration |
| #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 |
| chip northbridge/amd/amdk8/root_complex |
| device apic_cluster 0 on |
| chip cpu/amd/socket_AM2 |
| device apic 0 on end |
| end |
| end |
| device pci_domain 0 on |
| chip northbridge/amd/amdk8 |
| device pci 18.0 on # southbridge, K8 HT Configuration |
| chip southbridge/amd/rs690 |
| device pci 0.0 on end # HT 0x7910 |
| # device pci 0.1 off end # CLK |
| device pci 1.0 on # Internal Graphics P2P bridge 0x7912 |
| chip drivers/pci/onboard |
| device pci 5.0 on end # Internal Graphics 0x791F |
| end |
| end |
| device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 |
| device pci 3.0 off end # PCIE P2P bridge 0x791b |
| device pci 4.0 on end # PCIE P2P bridge 0x7914 |
| device pci 5.0 on end # PCIE P2P bridge 0x7915 |
| device pci 6.0 on end # PCIE P2P bridge 0x7916 |
| device pci 7.0 on end # PCIE P2P bridge 0x7917 |
| device pci 8.0 off end # NB/SB Link P2P bridge |
| register "gpp_configuration" = "4" |
| register "port_enable" = "0xfc" |
| register "gfx_dev2_dev3" = "1" |
| register "gfx_dual_slot" = "0" |
| register "gfx_lane_reversal" = "0" |
| register "gfx_tmds" = "0" |
| register "gfx_compliance" = "0" |
| register "gfx_reconfiguration" = "1" |
| register "gfx_link_width" = "0" |
| end |
| chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus |
| device pci 12.0 on end # SATA 0x4380 |
| device pci 13.0 on end # USB 0x4387 |
| device pci 13.1 on end # USB 0x4388 |
| device pci 13.2 on end # USB 0x4389 |
| device pci 13.3 on end # USB 0x438a |
| device pci 13.4 on end # USB 0x438b |
| device pci 13.5 on end # USB 2 0x4386 |
| device pci 14.0 on # SM 0x4385 |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 50 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 51 off end |
| end |
| chip drivers/generic/generic #dimm 0-1-0 |
| device i2c 52 off end |
| end |
| chip drivers/generic/generic #dimm 0-1-1 |
| device i2c 53 off end |
| end |
| end # SM |
| device pci 14.1 on end # IDE 0x438c |
| device pci 14.2 on end # HDA 0x4383 |
| device pci 14.3 on end # LPC 0x438d |
| device pci 14.4 on end # PCI 0x4384 |
| device pci 14.5 on end # ACI 0x4382 |
| device pci 14.6 on end # MCI 0x438e |
| register "ide0_enable" = "1" |
| register "sata0_enable" = "1" |
| register "hda_viddid" = "0x10ec0882" |
| end #southbridge/amd/sb600 |
| end # device pci 18.0 |
| |
| device pci 18.1 on end # K8 Address Map |
| device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode |
| device pci 18.3 on end # K8 Miscellaneous Control |
| end #northbridge/amd/amdk8 |
| end #pci_domain |
| end #northbridge/amd/amdk8/root_complex |
| |