| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| #include <console/console.h> |
| #include <device/device.h> |
| #include <device/pci.h> |
| #include <arch/cpu.h> |
| #include <cpu/cpu.h> |
| #include <cpu/x86/mtrr.h> |
| #include <cpu/x86/msr.h> |
| #include <cpu/x86/lapic.h> |
| #include <cpu/x86/mp.h> |
| #include <cpu/intel/microcode.h> |
| #include <cpu/intel/smm_reloc.h> |
| #include <cpu/intel/speedstep.h> |
| #include <cpu/intel/turbo.h> |
| #include <cpu/x86/name.h> |
| #include <delay.h> |
| #include <intelblocks/cpulib.h> |
| #include <soc/cpu.h> |
| #include <soc/msr.h> |
| #include <soc/pci_devs.h> |
| #include <soc/ramstage.h> |
| #include <soc/rcba.h> |
| #include <soc/systemagent.h> |
| #include <soc/intel/broadwell/chip.h> |
| #include <cpu/intel/common/common.h> |
| |
| /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate |
| * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly |
| * when a core is woken up. */ |
| static int pcode_ready(void) |
| { |
| int wait_count; |
| const int delay_step = 10; |
| |
| wait_count = 0; |
| do { |
| if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) |
| return 0; |
| wait_count += delay_step; |
| udelay(delay_step); |
| } while (wait_count < 1000); |
| |
| return -1; |
| } |
| |
| static void calibrate_24mhz_bclk(void) |
| { |
| int err_code; |
| |
| if (pcode_ready() < 0) { |
| printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| return; |
| } |
| |
| /* A non-zero value initiates the PCODE calibration. */ |
| MCHBAR32(BIOS_MAILBOX_DATA) = ~0; |
| MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; |
| |
| if (pcode_ready() < 0) { |
| printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| return; |
| } |
| |
| err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; |
| |
| printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", |
| err_code); |
| |
| /* Read the calibrated value. */ |
| MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; |
| |
| if (pcode_ready() < 0) { |
| printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); |
| return; |
| } |
| |
| printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", |
| MCHBAR32(BIOS_MAILBOX_DATA)); |
| } |
| |
| static u32 pcode_mailbox_read(u32 command) |
| { |
| if (pcode_ready() < 0) { |
| printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| return 0; |
| } |
| |
| /* Send command and start transaction */ |
| MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; |
| |
| if (pcode_ready() < 0) { |
| printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| return 0; |
| } |
| |
| /* Read mailbox */ |
| return MCHBAR32(BIOS_MAILBOX_DATA); |
| } |
| |
| static int pcode_mailbox_write(u32 command, u32 data) |
| { |
| if (pcode_ready() < 0) { |
| printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| return -1; |
| } |
| |
| MCHBAR32(BIOS_MAILBOX_DATA) = data; |
| |
| /* Send command and start transaction */ |
| MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; |
| |
| if (pcode_ready() < 0) { |
| printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| return -1; |
| } |
| |
| return 0; |
| } |
| |
| static void initialize_vr_config(void) |
| { |
| config_t *conf = config_of_soc(); |
| msr_t msr; |
| |
| printk(BIOS_DEBUG, "Initializing VR config.\n"); |
| |
| /* Configure VR_CURRENT_CONFIG. */ |
| msr = rdmsr(MSR_VR_CURRENT_CONFIG); |
| /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid |
| * on ULT systems. */ |
| msr.hi &= 0xc0000000; |
| msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ |
| msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ |
| msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ |
| msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ |
| /* Leave the max instantaneous current limit (12:0) to default. */ |
| wrmsr(MSR_VR_CURRENT_CONFIG, msr); |
| |
| /* Configure VR_MISC_CONFIG MSR. */ |
| msr = rdmsr(MSR_VR_MISC_CONFIG); |
| /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ |
| msr.hi &= ~(0x3ff << (40 - 32)); |
| msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ |
| /* Set IOUT_OFFSET to 0. */ |
| msr.hi &= ~0xff; |
| /* Set entry ramp rate to slow. */ |
| msr.hi &= ~(1 << (51 - 32)); |
| /* Enable decay mode on C-state entry. */ |
| msr.hi |= (1 << (52 - 32)); |
| /* Set the slow ramp rate */ |
| msr.hi &= ~(0x3 << (53 - 32)); |
| /* Configure the C-state exit ramp rate. */ |
| if (conf->vr_slow_ramp_rate_enable) { |
| /* Configured slow ramp rate. */ |
| msr.hi |= ((conf->vr_slow_ramp_rate_set & 0x3) << (53 - 32)); |
| /* Set exit ramp rate to slow. */ |
| msr.hi &= ~(1 << (50 - 32)); |
| } else { |
| /* Fast ramp rate / 4. */ |
| msr.hi |= (0x01 << (53 - 32)); |
| /* Set exit ramp rate to fast. */ |
| msr.hi |= (1 << (50 - 32)); |
| } |
| /* Set MIN_VID (31:24) to allow CPU to have full control. */ |
| msr.lo &= ~0xff000000; |
| msr.lo |= (conf->vr_cpu_min_vid & 0xff) << 24; |
| wrmsr(MSR_VR_MISC_CONFIG, msr); |
| |
| /* Configure VR_MISC_CONFIG2 MSR. */ |
| msr = rdmsr(MSR_VR_MISC_CONFIG2); |
| msr.lo &= ~0xffff; |
| /* Allow CPU to control minimum voltage completely (15:8) and |
| * set the fast ramp voltage in 10mV steps. */ |
| if (cpu_family_model() == BROADWELL_FAMILY_ULT) |
| msr.lo |= 0x006a; /* 1.56V */ |
| else |
| msr.lo |= 0x006f; /* 1.60V */ |
| wrmsr(MSR_VR_MISC_CONFIG2, msr); |
| |
| /* Set C9/C10 VCC Min */ |
| pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); |
| } |
| |
| static void configure_pch_power_sharing(void) |
| { |
| u32 pch_power, pch_power_ext, pmsync, pmsync2; |
| int i; |
| |
| /* Read PCH Power levels from PCODE */ |
| pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); |
| pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); |
| |
| printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", |
| pch_power, pch_power_ext); |
| |
| pmsync = RCBA32(PMSYNC_CONFIG); |
| pmsync2 = RCBA32(PMSYNC_CONFIG2); |
| |
| /* Program PMSYNC_TPR_CONFIG PCH power limit values |
| * pmsync[0:4] = mailbox[0:5] |
| * pmsync[8:12] = mailbox[6:11] |
| * pmsync[16:20] = mailbox[12:17] |
| */ |
| for (i = 0; i < 3; i++) { |
| u32 level = pch_power & 0x3f; |
| pch_power >>= 6; |
| pmsync &= ~(0x1f << (i * 8)); |
| pmsync |= (level & 0x1f) << (i * 8); |
| } |
| RCBA32(PMSYNC_CONFIG) = pmsync; |
| |
| /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values |
| * pmsync2[0:4] = mailbox[23:18] |
| * pmsync2[8:12] = mailbox_ext[6:11] |
| * pmsync2[16:20] = mailbox_ext[12:17] |
| * pmsync2[24:28] = mailbox_ext[18:22] |
| */ |
| pmsync2 &= ~0x1f; |
| pmsync2 |= pch_power & 0x1f; |
| |
| for (i = 1; i < 4; i++) { |
| u32 level = pch_power_ext & 0x3f; |
| pch_power_ext >>= 6; |
| pmsync2 &= ~(0x1f << (i * 8)); |
| pmsync2 |= (level & 0x1f) << (i * 8); |
| } |
| RCBA32(PMSYNC_CONFIG2) = pmsync2; |
| } |
| |
| static void configure_c_states(void) |
| { |
| msr_t msr; |
| |
| msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
| msr.lo |= (1 << 31); // Timed MWAIT Enable |
| msr.lo |= (1 << 30); // Package c-state Undemotion Enable |
| msr.lo |= (1 << 29); // Package c-state Demotion Enable |
| msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
| /* The deepest package c-state defaults to factory-configured value. */ |
| wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
| |
| msr = rdmsr(MSR_MISC_PWR_MGMT); |
| msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| wrmsr(MSR_MISC_PWR_MGMT, msr); |
| |
| msr = rdmsr(MSR_POWER_CTL); |
| msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| msr.lo |= (1 << 1); // C1E Enable |
| msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| wrmsr(MSR_POWER_CTL, msr); |
| |
| /* C-state Interrupt Response Latency Control 0 - package C3 latency */ |
| msr.hi = 0; |
| msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; |
| wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); |
| |
| /* C-state Interrupt Response Latency Control 1 */ |
| msr.hi = 0; |
| msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
| wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
| |
| /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ |
| msr.hi = 0; |
| msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
| wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
| |
| /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| msr.hi = 0; |
| msr.lo = IRTL_VALID | IRTL_1024_NS | |
| C_STATE_LATENCY_CONTROL_3_LIMIT; |
| wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
| |
| /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| msr.hi = 0; |
| msr.lo = IRTL_VALID | IRTL_1024_NS | |
| C_STATE_LATENCY_CONTROL_4_LIMIT; |
| wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| |
| /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| msr.hi = 0; |
| msr.lo = IRTL_VALID | IRTL_1024_NS | |
| C_STATE_LATENCY_CONTROL_5_LIMIT; |
| wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
| } |
| |
| static void configure_misc(void) |
| { |
| msr_t msr; |
| |
| msr = rdmsr(IA32_MISC_ENABLE); |
| msr.lo |= (1 << 0); /* Fast String enable */ |
| msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| wrmsr(IA32_MISC_ENABLE, msr); |
| |
| /* Disable Thermal interrupts */ |
| msr.lo = 0; |
| msr.hi = 0; |
| wrmsr(IA32_THERM_INTERRUPT, msr); |
| |
| /* Enable package critical interrupt only */ |
| msr.lo = 1 << 4; |
| msr.hi = 0; |
| wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| } |
| |
| static void enable_lapic_tpr(void) |
| { |
| msr_t msr; |
| |
| msr = rdmsr(MSR_PIC_MSG_CONTROL); |
| msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ |
| wrmsr(MSR_PIC_MSG_CONTROL, msr); |
| } |
| |
| static void configure_dca_cap(void) |
| { |
| uint32_t feature_flag; |
| msr_t msr; |
| |
| /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ |
| feature_flag = cpu_get_feature_flags_ecx(); |
| if (feature_flag & CPUID_DCA) { |
| msr = rdmsr(IA32_PLATFORM_DCA_CAP); |
| msr.lo |= 1; |
| wrmsr(IA32_PLATFORM_DCA_CAP, msr); |
| } |
| } |
| |
| static void set_max_ratio(void) |
| { |
| msr_t msr, perf_ctl; |
| |
| perf_ctl.hi = 0; |
| |
| /* Check for configurable TDP option */ |
| if (get_turbo_state() == TURBO_ENABLED) { |
| msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| perf_ctl.lo = (msr.lo & 0xff) << 8; |
| } else if (cpu_config_tdp_levels()) { |
| /* Set to nominal TDP ratio */ |
| msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| perf_ctl.lo = (msr.lo & 0xff) << 8; |
| } else { |
| /* Platform Info bits 15:8 give max ratio */ |
| msr = rdmsr(MSR_PLATFORM_INFO); |
| perf_ctl.lo = msr.lo & 0xff00; |
| } |
| wrmsr(IA32_PERF_CTL, perf_ctl); |
| |
| printk(BIOS_DEBUG, "CPU: frequency set to %d\n", |
| ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); |
| } |
| |
| static void set_energy_perf_bias(u8 policy) |
| { |
| msr_t msr; |
| int ecx; |
| |
| /* Determine if energy efficient policy is supported. */ |
| ecx = cpuid_ecx(0x6); |
| if (!(ecx & (1 << 3))) |
| return; |
| |
| /* Energy Policy is bits 3:0 */ |
| msr = rdmsr(IA32_ENERGY_PERF_BIAS); |
| msr.lo &= ~0xf; |
| msr.lo |= policy & 0xf; |
| wrmsr(IA32_ENERGY_PERF_BIAS, msr); |
| |
| printk(BIOS_DEBUG, "CPU: energy policy set to %u\n", policy); |
| } |
| |
| static void configure_mca(void) |
| { |
| msr_t msr; |
| int i; |
| int num_banks; |
| |
| msr = rdmsr(IA32_MCG_CAP); |
| num_banks = msr.lo & 0xff; |
| msr.lo = msr.hi = 0; |
| /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| * of these banks are core vs package scope. For now every CPU clears |
| * every bank. */ |
| for (i = 0; i < num_banks; i++) |
| wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
| } |
| |
| /* All CPUs including BSP will run the following function. */ |
| static void cpu_core_init(struct device *cpu) |
| { |
| /* Clear out pending MCEs */ |
| configure_mca(); |
| |
| /* Enable the local CPU apics */ |
| enable_lapic_tpr(); |
| setup_lapic(); |
| |
| /* Set virtualization based on Kconfig option */ |
| set_vmx_and_lock(); |
| |
| /* Configure C States */ |
| configure_c_states(); |
| |
| /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| configure_misc(); |
| |
| /* Thermal throttle activation offset */ |
| configure_tcc_thermal_target(); |
| |
| /* Enable Direct Cache Access */ |
| configure_dca_cap(); |
| |
| /* Set energy policy */ |
| set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| |
| /* Enable Turbo */ |
| enable_turbo(); |
| } |
| |
| /* MP initialization support. */ |
| static const void *microcode_patch; |
| |
| static void pre_mp_init(void) |
| { |
| /* Setup MTRRs based on physical address size. */ |
| x86_setup_mtrrs_with_detect(); |
| x86_mtrr_check(); |
| |
| initialize_vr_config(); |
| calibrate_24mhz_bclk(); |
| configure_pch_power_sharing(); |
| } |
| |
| static int get_cpu_count(void) |
| { |
| msr_t msr; |
| int num_threads; |
| int num_cores; |
| |
| msr = rdmsr(MSR_CORE_THREAD_COUNT); |
| num_threads = (msr.lo >> 0) & 0xffff; |
| num_cores = (msr.lo >> 16) & 0xffff; |
| printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| num_cores, num_threads); |
| |
| return num_threads; |
| } |
| |
| static void get_microcode_info(const void **microcode, int *parallel) |
| { |
| microcode_patch = intel_microcode_find(); |
| *microcode = microcode_patch; |
| *parallel = 1; |
| } |
| |
| static void per_cpu_smm_trigger(void) |
| { |
| /* Relocate the SMM handler. */ |
| smm_relocate(); |
| |
| /* After SMM relocation a 2nd microcode load is required. */ |
| intel_microcode_load_unlocked(microcode_patch); |
| } |
| |
| static void post_mp_init(void) |
| { |
| /* Set Max Ratio */ |
| set_max_ratio(); |
| |
| /* Now that all APs have been relocated as well as the BSP let SMIs |
| * start flowing. */ |
| global_smi_enable(); |
| |
| /* Lock down the SMRAM space. */ |
| smm_lock(); |
| } |
| |
| static const struct mp_ops mp_ops = { |
| .pre_mp_init = pre_mp_init, |
| .get_cpu_count = get_cpu_count, |
| .get_smm_info = smm_info, |
| .get_microcode_info = get_microcode_info, |
| .pre_mp_smm_init = smm_initialize, |
| .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| .relocation_handler = smm_relocation_handler, |
| .post_mp_init = post_mp_init, |
| }; |
| |
| void broadwell_init_cpus(struct device *dev) |
| { |
| struct bus *cpu_bus = dev->link_list; |
| |
| if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| printk(BIOS_ERR, "MP initialization failure.\n"); |
| } |
| |
| static struct device_operations cpu_dev_ops = { |
| .init = cpu_core_init, |
| }; |
| |
| static const struct cpu_device_id cpu_table[] = { |
| { X86_VENDOR_INTEL, CPUID_HASWELL_ULT }, |
| { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, |
| { X86_VENDOR_INTEL, CPUID_BROADWELL_D0 }, |
| { X86_VENDOR_INTEL, CPUID_BROADWELL_E0 }, |
| { 0, 0 }, |
| }; |
| |
| static const struct cpu_driver driver __cpu_driver = { |
| .ops = &cpu_dev_ops, |
| .id_table = cpu_table, |
| }; |