| # CFG Version 06 |
| # Do not edit. Generated by t210_emc_reg_tool_P972.exe V9.7.2. Command: |
| # t210_emc_reg_tool_P972.exe -i E2581_3GB.par 04.90196078431372549019 -dram_board_cfg 33 |
| # -data_bus_to_0 1 -fly_by_time_ps 1700 -dbi_rd_en 1 -is_bkv 1 -t T210_DSC_E2581A00_lpddr4_tbkv_est_072514.txt |
| # -o E2581_A00_3GB_P972_configs\E2581_A00_3GB_Samsung_4GB_lpddr4_204Mhz_P972_v1.cfg |
| # Parameter file: E2581_3GB.par, tck = 4.90 ns (204.00 MHz) |
| SDRAM[0].MemoryType = NvBootMemoryType_LpDdr4; |
| SDRAM[0].PllMInputDivider = 0x00000001; |
| SDRAM[0].PllMFeedbackDivider = 0x00000022; |
| SDRAM[0].PllMStableTime = 0x0000012c; |
| SDRAM[0].PllMSetupControl = 0x00000000; |
| SDRAM[0].PllMPostDivider = 0x00000000; |
| SDRAM[0].PllMKCP = 0x00000000; |
| SDRAM[0].PllMKVCO = 0x00000000; |
| SDRAM[0].EmcBctSpare0 = 0x00000000; |
| SDRAM[0].EmcBctSpare1 = 0x00000000; |
| SDRAM[0].EmcBctSpare2 = 0x00000000; |
| SDRAM[0].EmcBctSpare3 = 0x00000000; |
| SDRAM[0].EmcBctSpare4 = 0x7001bc3c; |
| SDRAM[0].EmcBctSpare5 = 0x00000032; |
| SDRAM[0].EmcBctSpare6 = 0x7001b404; |
| SDRAM[0].EmcBctSpare7 = 0x71245603; |
| SDRAM[0].EmcBctSpare8 = 0x7000e6c8; |
| SDRAM[0].EmcBctSpare9 = 0x00000000; |
| SDRAM[0].EmcBctSpare10 = 0x00000000; |
| SDRAM[0].EmcBctSpare11 = 0x00000000; |
| SDRAM[0].EmcBctSpare12 = 0x7001bc3c; |
| SDRAM[0].EmcBctSpare13 = 0x00000033; |
| SDRAM[0].EmcClockSource = 0x40188002; |
| SDRAM[0].EmcClockSourceDll = 0x40000000; |
| SDRAM[0].ClkRstControllerPllmMisc2Override = 0x00000000; |
| SDRAM[0].ClkRstControllerPllmMisc2OverrideEnable = 0x00000000; |
| SDRAM[0].ClearClk2Mc1 = 0x00000000; |
| SDRAM[0].EmcAutoCalInterval = 0x001fffff; |
| SDRAM[0].EmcAutoCalConfig = 0xa01a51d8; |
| SDRAM[0].EmcAutoCalConfig2 = 0x05500000; |
| SDRAM[0].EmcAutoCalConfig3 = 0x00770000; |
| SDRAM[0].EmcAutoCalConfig4 = 0x00770000; |
| SDRAM[0].EmcAutoCalConfig5 = 0x00770000; |
| SDRAM[0].EmcAutoCalConfig6 = 0x00770000; |
| SDRAM[0].EmcAutoCalConfig7 = 0x00770000; |
| SDRAM[0].EmcAutoCalConfig8 = 0x00770000; |
| SDRAM[0].EmcAutoCalVrefSel0 = 0xb3afa6a6; |
| SDRAM[0].EmcAutoCalVrefSel1 = 0x00009e3c; |
| SDRAM[0].EmcAutoCalChannel = 0xc1e00303; |
| SDRAM[0].EmcPmacroAutocalCfg0 = 0x04040404; |
| SDRAM[0].EmcPmacroAutocalCfg1 = 0x04040404; |
| SDRAM[0].EmcPmacroAutocalCfg2 = 0x00000000; |
| SDRAM[0].EmcPmacroRxTerm = 0x1f1f1f1f; |
| SDRAM[0].EmcPmacroDqTxDrv = 0x1f1f1f1f; |
| SDRAM[0].EmcPmacroCaTxDrv = 0x1f1f1f1f; |
| SDRAM[0].EmcPmacroCmdTxDrv = 0x00001f1f; |
| SDRAM[0].EmcPmacroAutocalCfgCommon = 0x00000804; |
| SDRAM[0].EmcPmacroZctrl = 0x00000550; |
| SDRAM[0].EmcAutoCalWait = 0x000001a1; |
| SDRAM[0].EmcXm2CompPadCtrl = 0x00000032; |
| SDRAM[0].EmcXm2CompPadCtrl2 = 0x00000000; |
| SDRAM[0].EmcXm2CompPadCtrl3 = 0x00000000; |
| SDRAM[0].EmcAdrCfg = 0x00000001; |
| SDRAM[0].EmcPinProgramWait = 0x00000002; |
| SDRAM[0].EmcPinExtraWait = 0x00000000; |
| SDRAM[0].EmcPinGpioEn = 0x00000003; |
| SDRAM[0].EmcPinGpio = 0x00000003; |
| SDRAM[0].EmcTimingControlWait = 0x0000001e; |
| SDRAM[0].EmcRc = 0x0000000d; |
| SDRAM[0].EmcRfc = 0x00000025; |
| SDRAM[0].EmcRfcPb = 0x00000013; |
| SDRAM[0].EmcRefctrl2 = 0x00000000; |
| SDRAM[0].EmcRfcSlr = 0x00000000; |
| SDRAM[0].EmcRas = 0x00000009; |
| SDRAM[0].EmcRp = 0x00000004; |
| SDRAM[0].EmcR2r = 0x00000000; |
| SDRAM[0].EmcW2w = 0x00000000; |
| SDRAM[0].EmcR2w = 0x0000000b; |
| SDRAM[0].EmcW2r = 0x0000000d; |
| SDRAM[0].EmcR2p = 0x00000008; |
| SDRAM[0].EmcW2p = 0x0000000b; |
| SDRAM[0].EmcTppd = 0x00000004; |
| SDRAM[0].EmcCcdmw = 0x00000020; |
| SDRAM[0].EmcRdRcd = 0x00000006; |
| SDRAM[0].EmcWrRcd = 0x00000006; |
| SDRAM[0].EmcRrd = 0x00000006; |
| SDRAM[0].EmcRext = 0x00000003; |
| SDRAM[0].EmcWext = 0x00000000; |
| SDRAM[0].EmcWdv = 0x00000004; |
| SDRAM[0].EmcWdvChk = 0x00000006; |
| SDRAM[0].EmcWsv = 0x00000002; |
| SDRAM[0].EmcWev = 0x00000000; |
| SDRAM[0].EmcWdvMask = 0x00000004; |
| SDRAM[0].EmcWsDuration = 0x00000008; |
| SDRAM[0].EmcWeDuration = 0x0000000d; |
| SDRAM[0].EmcQUse = 0x00000005; |
| SDRAM[0].EmcQuseWidth = 0x00000006; |
| SDRAM[0].EmcIbdly = 0x00000000; |
| SDRAM[0].EmcObdly = 0x00000000; |
| SDRAM[0].EmcEInput = 0x00000002; |
| SDRAM[0].EmcEInputDuration = 0x0000000d; |
| SDRAM[0].EmcPutermExtra = 0x00000002; |
| SDRAM[0].EmcPutermWidth = 0x0000000b; |
| SDRAM[0].EmcQRst = 0x00010000; |
| SDRAM[0].EmcQSafe = 0x00000012; |
| SDRAM[0].EmcRdv = 0x00000014; |
| SDRAM[0].EmcRdvMask = 0x00000016; |
| SDRAM[0].EmcRdvEarly = 0x00000012; |
| SDRAM[0].EmcRdvEarlyMask = 0x00000014; |
| SDRAM[0].EmcQpop = 0x0000000a; |
| SDRAM[0].EmcRefresh = 0x00000304; |
| SDRAM[0].EmcBurstRefreshNum = 0x00000000; |
| SDRAM[0].EmcPreRefreshReqCnt = 0x000000c1; |
| SDRAM[0].EmcPdEx2Wr = 0x00000008; |
| SDRAM[0].EmcPdEx2Rd = 0x00000008; |
| SDRAM[0].EmcPChg2Pden = 0x00000003; |
| SDRAM[0].EmcAct2Pden = 0x00000003; |
| SDRAM[0].EmcAr2Pden = 0x00000003; |
| SDRAM[0].EmcRw2Pden = 0x00000012; |
| SDRAM[0].EmcCke2Pden = 0x00000005; |
| SDRAM[0].EmcPdex2Cke = 0x00000002; |
| SDRAM[0].EmcPdex2Mrr = 0x0000000d; |
| SDRAM[0].EmcTxsr = 0x00000027; |
| SDRAM[0].EmcTxsrDll = 0x00000027; |
| SDRAM[0].EmcTcke = 0x00000005; |
| SDRAM[0].EmcTckesr = 0x00000005; |
| SDRAM[0].EmcTpd = 0x00000004; |
| SDRAM[0].EmcTfaw = 0x00000009; |
| SDRAM[0].EmcTrpab = 0x00000005; |
| SDRAM[0].EmcTClkStable = 0x00000003; |
| SDRAM[0].EmcTClkStop = 0x00000009; |
| SDRAM[0].EmcTRefBw = 0x0000031c; |
| SDRAM[0].EmcFbioCfg5 = 0x9160a00d; |
| SDRAM[0].EmcFbioCfg7 = 0x00003bbf; |
| SDRAM[0].EmcFbioCfg8 = 0x0cf30000; |
| SDRAM[0].EmcCmdMappingCmd0_0 = 0x07050203; |
| SDRAM[0].EmcCmdMappingCmd0_1 = 0x06041b1c; |
| SDRAM[0].EmcCmdMappingCmd0_2 = 0x05252523; |
| SDRAM[0].EmcCmdMappingCmd1_0 = 0x1e0d0b0a; |
| SDRAM[0].EmcCmdMappingCmd1_1 = 0x240c091d; |
| SDRAM[0].EmcCmdMappingCmd1_2 = 0x04262608; |
| SDRAM[0].EmcCmdMappingCmd2_0 = 0x051b0302; |
| SDRAM[0].EmcCmdMappingCmd2_1 = 0x0604231c; |
| SDRAM[0].EmcCmdMappingCmd2_2 = 0x09252507; |
| SDRAM[0].EmcCmdMappingCmd3_0 = 0x0c0b0d0a; |
| SDRAM[0].EmcCmdMappingCmd3_1 = 0x08091e1d; |
| SDRAM[0].EmcCmdMappingCmd3_2 = 0x08262624; |
| SDRAM[0].EmcCmdMappingByte = 0x0a270623; |
| SDRAM[0].EmcFbioSpare = 0x00000012; |
| SDRAM[0].EmcCfgRsv = 0xff00ff00; |
| SDRAM[0].EmcMrs = 0x00000000; |
| SDRAM[0].EmcEmrs = 0x00000000; |
| SDRAM[0].EmcEmrs2 = 0x00000000; |
| SDRAM[0].EmcEmrs3 = 0x00000000; |
| SDRAM[0].EmcMrw1 = 0x08010004; |
| SDRAM[0].EmcMrw2 = 0x08020000; |
| SDRAM[0].EmcMrw3 = 0x080d0000; |
| SDRAM[0].EmcMrw4 = 0xc0000000; |
| SDRAM[0].EmcMrw6 = 0x08037171; |
| SDRAM[0].EmcMrw8 = 0x080b0000; |
| SDRAM[0].EmcMrw9 = 0x0c0e6b6b; |
| SDRAM[0].EmcMrw10 = 0x00000000; |
| SDRAM[0].EmcMrw12 = 0x0c0d0808; |
| SDRAM[0].EmcMrw13 = 0x0c0d0000; |
| SDRAM[0].EmcMrw14 = 0x08161414; |
| SDRAM[0].EmcMrwExtra = 0x08010004; |
| SDRAM[0].EmcWarmBootMrwExtra = 0x08110000; |
| SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000001; |
| SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[0].EmcMrwResetCommand = 0x00000000; |
| SDRAM[0].EmcMrwResetNInitWait = 0x00000000; |
| SDRAM[0].EmcMrsWaitCnt = 0x00cc0015; |
| SDRAM[0].EmcMrsWaitCnt2 = 0x0033000a; |
| SDRAM[0].EmcCfg = 0xf3200000; |
| SDRAM[0].EmcCfg2 = 0x00110805; |
| SDRAM[0].EmcCfgPipe = 0x0fff0fff; |
| SDRAM[0].EmcCfgPipeClk = 0x00000000; |
| SDRAM[0].EmcFdpdCtrlCmdNoRamp = 0x00000001; |
| SDRAM[0].EmcCfgUpdate = 0x70000301; |
| SDRAM[0].EmcDbg = 0x01000c00; |
| SDRAM[0].EmcDbgWriteMux = 0x00000001; |
| SDRAM[0].EmcCmdQ = 0x10004408; |
| SDRAM[0].EmcMc2EmcQ = 0x06000404; |
| SDRAM[0].EmcDynSelfRefControl = 0x80000713; |
| SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; |
| SDRAM[0].EmcCfgDigDll = 0x002c00a0; |
| SDRAM[0].EmcCfgDigDll_1 = 0x00003701; |
| SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; |
| SDRAM[0].EmcDevSelect = 0x00000000; |
| SDRAM[0].EmcSelDpdCtrl = 0x00040008; |
| SDRAM[0].EmcFdpdCtrlDq = 0x8020221f; |
| SDRAM[0].EmcFdpdCtrlCmd = 0x0220f40f; |
| SDRAM[0].EmcPmacroIbVrefDq_0 = 0x28282828; |
| SDRAM[0].EmcPmacroIbVrefDq_1 = 0x28282828; |
| SDRAM[0].EmcPmacroIbVrefDqs_0 = 0x11111111; |
| SDRAM[0].EmcPmacroIbVrefDqs_1 = 0x11111111; |
| SDRAM[0].EmcPmacroIbRxrt = 0x000000be; |
| SDRAM[0].EmcCfgPipe1 = 0x0fff0fff; |
| SDRAM[0].EmcCfgPipe2 = 0x0fff0fff; |
| SDRAM[0].EmcPmacroQuseDdllRank0_0 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank0_1 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank0_2 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank0_3 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank0_4 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank0_5 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank1_0 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank1_1 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank1_2 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank1_3 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank1_4 = 0x00000000; |
| SDRAM[0].EmcPmacroQuseDdllRank1_5 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank0_0 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank0_1 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank0_2 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank0_3 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank0_4 = 0x00080007; |
| SDRAM[0].EmcPmacroObDdllLongDqRank0_5 = 0x00090006; |
| SDRAM[0].EmcPmacroObDdllLongDqRank1_0 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank1_1 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank1_2 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank1_3 = 0x00000000; |
| SDRAM[0].EmcPmacroObDdllLongDqRank1_4 = 0x00080007; |
| SDRAM[0].EmcPmacroObDdllLongDqRank1_5 = 0x00090006; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank0_0 = 0x00340033; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank0_1 = 0x00340037; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank0_2 = 0x00360037; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank0_3 = 0x00330036; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank0_4 = 0x000a000c; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank0_5 = 0x000d000a; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank1_0 = 0x00340033; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank1_1 = 0x00340037; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank1_2 = 0x00360037; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank1_3 = 0x00330036; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank1_4 = 0x000a000c; |
| SDRAM[0].EmcPmacroObDdllLongDqsRank1_5 = 0x000d000a; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank0_0 = 0x00F000F0; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank0_1 = 0x00F000F0; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank0_2 = 0x00F000F0; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank0_3 = 0x00F000F0; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank1_0 = 0x00F000F0; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank1_1 = 0x00F000F0; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank1_2 = 0x00F000F0; |
| SDRAM[0].EmcPmacroIbDdllLongDqsRank1_3 = 0x00F000F0; |
| SDRAM[0].EmcPmacroDdllLongCmd_0 = 0x00070007; |
| SDRAM[0].EmcPmacroDdllLongCmd_1 = 0x00080008; |
| SDRAM[0].EmcPmacroDdllLongCmd_2 = 0x00060006; |
| SDRAM[0].EmcPmacroDdllLongCmd_3 = 0x00090009; |
| SDRAM[0].EmcPmacroDdllLongCmd_4 = 0x00000007; |
| SDRAM[0].EmcPmacroDdllShortCmd_0 = 0x00000000; |
| SDRAM[0].EmcPmacroDdllShortCmd_1 = 0x00000000; |
| SDRAM[0].EmcPmacroDdllShortCmd_2 = 0x00000000; |
| SDRAM[0].WarmBootWait = 0x00000001; |
| SDRAM[0].EmcOdtWrite = 0x00000000; |
| SDRAM[0].EmcZcalInterval = 0x00064000; |
| SDRAM[0].EmcZcalWaitCnt = 0x000900cc; |
| SDRAM[0].EmcZcalMrwCmd = 0x0051004f; |
| SDRAM[0].EmcMrsResetDll = 0x00000000; |
| SDRAM[0].EmcZcalInitDev0 = 0x80000001; |
| SDRAM[0].EmcZcalInitDev1 = 0x40000001; |
| SDRAM[0].EmcZcalInitWait = 0x00000001; |
| SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; |
| SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; |
| SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000011; |
| SDRAM[0].EmcZqCalLpDdr4WarmBoot = 0x00000001; |
| SDRAM[0].EmcZcalWarmBootWait = 0x00000001; |
| SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; |
| SDRAM[0].EmcMrsResetDllWait = 0x00000000; |
| SDRAM[0].EmcMrsExtra = 0x00000000; |
| SDRAM[0].EmcWarmBootMrsExtra = 0x00000000; |
| SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; |
| SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; |
| SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; |
| SDRAM[0].EmcDdr2Wait = 0x00000000; |
| SDRAM[0].EmcClkenOverride = 0x00000000; |
| SDRAM[0].EmcExtraRefreshNum = 0x00000002; |
| SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; |
| SDRAM[0].PmcVddpSel = 0x00000001; |
| SDRAM[0].PmcVddpSelWait = 0x00000002; |
| SDRAM[0].PmcDdrPwr = 0x0000000f; |
| SDRAM[0].PmcDdrCfg = 0x20120100; |
| SDRAM[0].PmcIoDpd3Req = 0x4befffff; |
| SDRAM[0].PmcIoDpd3ReqWait = 0x00000001; |
| SDRAM[0].PmcIoDpd4ReqWait = 0x00000002; |
| SDRAM[0].PmcRegShort = 0x00000000; |
| SDRAM[0].PmcNoIoPower = 0x00000000; |
| SDRAM[0].PmcDdrCntrlWait = 0x00000000; |
| SDRAM[0].PmcDdrCntrl = 0x0007ff8b; |
| SDRAM[0].EmcAcpdControl = 0x00000000; |
| SDRAM[0].EmcSwizzleRank0Byte0 = 0x71245603; |
| SDRAM[0].EmcSwizzleRank0Byte1 = 0x16243705; |
| SDRAM[0].EmcSwizzleRank0Byte2 = 0x12574630; |
| SDRAM[0].EmcSwizzleRank0Byte3 = 0x26147503; |
| SDRAM[0].EmcSwizzleRank1Byte0 = 0x71345602; |
| SDRAM[0].EmcSwizzleRank1Byte1 = 0x20456713; |
| SDRAM[0].EmcSwizzleRank1Byte2 = 0x64071325; |
| SDRAM[0].EmcSwizzleRank1Byte3 = 0x54023167; |
| SDRAM[0].EmcTxdsrvttgen = 0x00000000; |
| SDRAM[0].EmcDataBrlshft0 = 0x00249249; |
| SDRAM[0].EmcDataBrlshft1 = 0x00249249; |
| SDRAM[0].EmcDqsBrlshft0 = 0x00000000; |
| SDRAM[0].EmcDqsBrlshft1 = 0x00000000; |
| SDRAM[0].EmcCmdBrlshft0 = 0x00000000; |
| SDRAM[0].EmcCmdBrlshft1 = 0x00000000; |
| SDRAM[0].EmcCmdBrlshft2 = 0x00000012; |
| SDRAM[0].EmcCmdBrlshft3 = 0x00000012; |
| SDRAM[0].EmcQuseBrlshft0 = 0x00000000; |
| SDRAM[0].EmcQuseBrlshft1 = 0x00000000; |
| SDRAM[0].EmcQuseBrlshft2 = 0x00000000; |
| SDRAM[0].EmcQuseBrlshft3 = 0x00000000; |
| SDRAM[0].EmcDllCfg0 = 0x1f13412f; |
| SDRAM[0].EmcDllCfg1 = 0x00010014; |
| SDRAM[0].EmcPmcScratch1 = 0x4befffff; |
| SDRAM[0].EmcPmcScratch2 = 0x7fffffff; |
| SDRAM[0].EmcPmcScratch3 = 0x4005d70b; |
| SDRAM[0].EmcPmacroPadCfgCtrl = 0x00020000; |
| SDRAM[0].EmcPmacroVttgenCtrl0 = 0x00030808; |
| SDRAM[0].EmcPmacroVttgenCtrl1 = 0x00015000; |
| SDRAM[0].EmcPmacroVttgenCtrl2 = 0x00101010; |
| SDRAM[0].EmcPmacroBrickCtrlRfu1 = 0x00001600; |
| SDRAM[0].EmcPmacroCmdBrickCtrlFdpd = 0x00000000; |
| SDRAM[0].EmcPmacroBrickCtrlRfu2 = 0x00000000; |
| SDRAM[0].EmcPmacroDataBrickCtrlFdpd = 0x00000000; |
| SDRAM[0].EmcPmacroBgBiasCtrl0 = 0x00000030; |
| SDRAM[0].EmcPmacroDataPadRxCtrl = 0x10050037; |
| SDRAM[0].EmcPmacroCmdPadRxCtrl = 0x00000000; |
| SDRAM[0].EmcPmacroDataRxTermMode = 0x00000010; |
| SDRAM[0].EmcPmacroCmdRxTermMode = 0x00003000; |
| SDRAM[0].EmcPmacroDataPadTxCtrl = 0x02000111; |
| SDRAM[0].EmcPmacroCommonPadTxCtrl = 0x00000008; |
| SDRAM[0].EmcPmacroCmdPadTxCtrl = 0x0a000000; |
| SDRAM[0].EmcCfg3 = 0x00000040; |
| SDRAM[0].EmcPmacroTxPwrd0 = 0x10000000; |
| SDRAM[0].EmcPmacroTxPwrd1 = 0x08000000; |
| SDRAM[0].EmcPmacroTxPwrd2 = 0x10000000; |
| SDRAM[0].EmcPmacroTxPwrd3 = 0x08000000; |
| SDRAM[0].EmcPmacroTxPwrd4 = 0x00000000; |
| SDRAM[0].EmcPmacroTxPwrd5 = 0x00000000; |
| SDRAM[0].EmcConfigSampleDelay = 0x00000020; |
| SDRAM[0].EmcPmacroBrickMapping0 = 0x28190081; |
| SDRAM[0].EmcPmacroBrickMapping1 = 0x44853293; |
| SDRAM[0].EmcPmacroBrickMapping2 = 0x76a76a5b; |
| SDRAM[0].EmcPmacroTxSelClkSrc0 = 0x00000000; |
| SDRAM[0].EmcPmacroTxSelClkSrc1 = 0x00000000; |
| SDRAM[0].EmcPmacroTxSelClkSrc2 = 0x00000000; |
| SDRAM[0].EmcPmacroTxSelClkSrc3 = 0x00000000; |
| SDRAM[0].EmcPmacroTxSelClkSrc4 = 0x00000000; |
| SDRAM[0].EmcPmacroTxSelClkSrc5 = 0x00000000; |
| SDRAM[0].EmcPmacroDdllBypass = 0xefffefff; |
| SDRAM[0].EmcPmacroDdllPwrd0 = 0xc0c0c0c0; |
| SDRAM[0].EmcPmacroDdllPwrd1 = 0xc0c0c0c0; |
| SDRAM[0].EmcPmacroDdllPwrd2 = 0xdcdcdcdc; |
| SDRAM[0].EmcPmacroCmdCtrl0 = 0x0a0a0a0a; |
| SDRAM[0].EmcPmacroCmdCtrl1 = 0x0a0a0a0a; |
| SDRAM[0].EmcPmacroCmdCtrl2 = 0x0a0a0a0a; |
| SDRAM[0].McEmemAdrCfg = 0x00000001; |
| SDRAM[0].McEmemAdrCfgDev0 = 0x000d0302; |
| SDRAM[0].McEmemAdrCfgDev1 = 0x000d0302; |
| SDRAM[0].McEmemAdrCfgChannelMask = 0xffff2400; |
| SDRAM[0].McEmemAdrCfgBankMask0 = 0x6e574400; |
| SDRAM[0].McEmemAdrCfgBankMask1 = 0x39722800; |
| SDRAM[0].McEmemAdrCfgBankMask2 = 0x4b9c1000; |
| SDRAM[0].McEmemCfg = 0x00000c00; |
| SDRAM[0].McEmemArbCfg = 0x08000001; |
| SDRAM[0].McEmemArbOutstandingReq = 0x8000004c; |
| SDRAM[0].McEmemArbRefpbHpCtrl = 0x000a1020; |
| SDRAM[0].McEmemArbRefpbBankCtrl = 0x80001028; |
| SDRAM[0].McEmemArbTimingRcd = 0x00000001; |
| SDRAM[0].McEmemArbTimingRp = 0x00000000; |
| SDRAM[0].McEmemArbTimingRc = 0x00000003; |
| SDRAM[0].McEmemArbTimingRas = 0x00000001; |
| SDRAM[0].McEmemArbTimingFaw = 0x00000002; |
| SDRAM[0].McEmemArbTimingRrd = 0x00000001; |
| SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002; |
| SDRAM[0].McEmemArbTimingWap2Pre = 0x00000005; |
| SDRAM[0].McEmemArbTimingR2R = 0x00000001; |
| SDRAM[0].McEmemArbTimingW2W = 0x00000001; |
| SDRAM[0].McEmemArbTimingR2W = 0x00000004; |
| SDRAM[0].McEmemArbTimingW2R = 0x00000005; |
| SDRAM[0].McEmemArbTimingRFCPB = 0x00000004; |
| SDRAM[0].McEmemArbDaTurns = 0x02020000; |
| SDRAM[0].McEmemArbDaCovers = 0x00030201; |
| SDRAM[0].McEmemArbMisc0 = 0x71c30504; |
| SDRAM[0].McEmemArbMisc1 = 0x70000f0f; |
| SDRAM[0].McEmemArbMisc2 = 0x00000000; |
| SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; |
| SDRAM[0].McEmemArbOverride = 0x10000000; |
| SDRAM[0].McEmemArbOverride1 = 0x00000000; |
| SDRAM[0].McEmemArbRsv = 0xff00ff00; |
| SDRAM[0].McDaCfg0 = 0x00000001; |
| SDRAM[0].McEmemArbTimingCcdmw = 0x00000008; |
| SDRAM[0].McClkenOverride = 0x00008000; |
| SDRAM[0].McStatControl = 0x00000000; |
| SDRAM[0].McVideoProtectBom = 0xfff00000; |
| SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; |
| SDRAM[0].McVideoProtectSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectVprOverride = 0xe4bac343; |
| SDRAM[0].McVideoProtectVprOverride1 = 0x00001ed3; |
| SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; |
| SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; |
| SDRAM[0].McSecCarveoutBom = 0xfff00000; |
| SDRAM[0].McSecCarveoutAdrHi = 0x00000000; |
| SDRAM[0].McSecCarveoutSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectWriteAccess = 0x00000000; |
| SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1Bom = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1BomHi = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1Size128kb = 0x00000008; |
| SDRAM[0].McGeneralizedCarveout1Access0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1Access1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1Access2 = 0x00300000; |
| SDRAM[0].McGeneralizedCarveout1Access3 = 0x03000000; |
| SDRAM[0].McGeneralizedCarveout1Access4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1ForceInternalAccess0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1ForceInternalAccess1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1ForceInternalAccess2 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1ForceInternalAccess3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1ForceInternalAccess4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout1Cfg0 = 0x04000c75; |
| SDRAM[0].McGeneralizedCarveout2Bom = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2BomHi = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2Size128kb = 0x00000002; |
| SDRAM[0].McGeneralizedCarveout2Access0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2Access1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2Access2 = 0x03000000; |
| SDRAM[0].McGeneralizedCarveout2Access3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2Access4 = 0x00000300; |
| SDRAM[0].McGeneralizedCarveout2ForceInternalAccess0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2ForceInternalAccess1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2ForceInternalAccess2 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2ForceInternalAccess3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2ForceInternalAccess4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout2Cfg0 = 0x0440167c; |
| SDRAM[0].McGeneralizedCarveout3Bom = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3BomHi = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3Size128kb = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3Access0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3Access1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3Access2 = 0x03000000; |
| SDRAM[0].McGeneralizedCarveout3Access3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3Access4 = 0x00000300; |
| SDRAM[0].McGeneralizedCarveout3ForceInternalAccess0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3ForceInternalAccess1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3ForceInternalAccess2 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3ForceInternalAccess3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3ForceInternalAccess4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout3Cfg0 = 0x04401e7c; |
| SDRAM[0].McGeneralizedCarveout4Bom = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4BomHi = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4Size128kb = 0x00000008; |
| SDRAM[0].McGeneralizedCarveout4Access0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4Access1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4Access2 = 0x00300000; |
| SDRAM[0].McGeneralizedCarveout4Access3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4Access4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4ForceInternalAccess0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4ForceInternalAccess1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout4Cfg0 = 0x04002442; |
| SDRAM[0].McGeneralizedCarveout5Bom = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5BomHi = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5Size128kb = 0x00000008; |
| SDRAM[0].McGeneralizedCarveout5Access0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5Access1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5Access2 = 0x00300000; |
| SDRAM[0].McGeneralizedCarveout5Access3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5Access4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5ForceInternalAccess0 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5ForceInternalAccess1 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000; |
| SDRAM[0].McGeneralizedCarveout5Cfg0 = 0x04002c42; |
| SDRAM[0].EmcCaTrainingEnable = 0x00000000; |
| SDRAM[0].SwizzleRankByteEncode = 0x0000000e; |
| SDRAM[0].BootRomPatchControl = 0x00000000; |
| SDRAM[0].BootRomPatchData = 0x00000000; |
| SDRAM[0].McMtsCarveoutBom = 0xfff00000; |
| SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; |
| SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; |
| SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 {0x7001b800} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 {0x7001b804} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 {0x7001b808} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 {0x7001b80c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 {0x7001b810} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 {0x7001b814} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 {0x7001b818} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 {0x7001b81c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 {0x7001b820} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 {0x7001b824} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 {0x7001b828} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 {0x7001b82c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 {0x7001b830} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 {0x7001b834} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 {0x7001b838} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 {0x7001b83c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 {0x7001b840} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 {0x7001b844} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 {0x7001b848} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 {0x7001b84c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 {0x7001b850} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 {0x7001b854} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 {0x7001b858} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 {0x7001b85c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 {0x7001b860} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 {0x7001b864} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 {0x7001b868} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 {0x7001b86c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 {0x7001b870} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 {0x7001b874} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 {0x7001b878} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 {0x7001b87c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 {0x7001b880} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 {0x7001b884} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 {0x7001b888} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 {0x7001b88c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 {0x7001b890} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 {0x7001b894} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 {0x7001b898} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 {0x7001b89c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 {0x7001b8a0} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 {0x7001b8a4} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 {0x7001b8a8} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 {0x7001b8ac} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 {0x7001b8b0} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 {0x7001b8b4} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 {0x7001b8b8} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 {0x7001b8bc} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 {0x7001b900} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 {0x7001b904} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 {0x7001b908} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 {0x7001b90c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 {0x7001b910} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 {0x7001b914} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 {0x7001b918} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 {0x7001b91c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 {0x7001b920} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 {0x7001b924} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 {0x7001b928} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 {0x7001b92c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 {0x7001b930} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 {0x7001b934} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 {0x7001b938} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 {0x7001b93c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 {0x7001b940} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 {0x7001b944} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 {0x7001b948} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 {0x7001b94c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 {0x7001b950} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 {0x7001b954} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 {0x7001b958} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 {0x7001b95c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 {0x7001b960} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 {0x7001b964} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 {0x7001b968} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 {0x7001b96c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 {0x7001b970} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 {0x7001b974} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 {0x7001b978} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 {0x7001b97c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 {0x7001b980} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 {0x7001b984} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 {0x7001b988} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 {0x7001b98c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 {0x7001b990} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 {0x7001b994} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 {0x7001b998} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 {0x7001b99c} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 {0x7001b9a0} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 {0x7001b9a4} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 {0x7001b9a8} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 {0x7001b9ac} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 {0x7001b9b0} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 {0x7001b9b4} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 {0x7001b9b8} = 0x00000000; |
| #@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 {0x7001b9bc} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 {0x7001ba00} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 {0x7001ba04} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 {0x7001ba08} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 {0x7001ba10} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 {0x7001ba14} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 {0x7001ba18} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 {0x7001ba20} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 {0x7001ba24} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 {0x7001ba28} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 {0x7001ba30} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 {0x7001ba34} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 {0x7001ba38} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 {0x7001ba40} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 {0x7001ba44} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 {0x7001ba48} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 {0x7001ba50} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 {0x7001ba54} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 {0x7001ba58} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 {0x7001ba60} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 {0x7001ba64} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 {0x7001ba68} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 {0x7001ba70} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 {0x7001ba74} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 {0x7001ba78} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 {0x7001bb00} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 {0x7001bb04} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 {0x7001bb08} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 {0x7001bb10} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 {0x7001bb14} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 {0x7001bb18} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 {0x7001bb20} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 {0x7001bb24} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 {0x7001bb28} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 {0x7001bb30} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 {0x7001bb34} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 {0x7001bb38} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 {0x7001bb40} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 {0x7001bb44} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 {0x7001bb48} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 {0x7001bb50} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 {0x7001bb54} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 {0x7001bb58} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 {0x7001bb60} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 {0x7001bb64} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 {0x7001bb68} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 {0x7001bb70} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 {0x7001bb74} = 0x00000000; |
| #@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 {0x7001bb78} = 0x00000000; |
| #@ EMC_TR_TIMING_0 {0x7001b3b4} = 0x01186033; |
| #@ EMC_TR_DVFS {0x7001b460} = 0x00000000; |
| #@ EMC_TR_CTRL_1 {0x7001b3bc} = 0x00000000; |
| #@ EMC_TR_RDV {0x7001b3c4} = 0x00000014; |
| #@ EMC_TR_QPOP {0x7001b3f4} = 0x0000000a; |
| #@ EMC_TR_RDV_MASK {0x7001b3f8} = 0x00000016; |
| #@ EMC_TR_QSAFE {0x7001b3fc} = 0x00000012; |
| #@ EMC_TR_QRST {0x7001b400} = 0x00010000; |
| #@ EMC_TRAINING_CTRL {0x7001be04} = 0x00009080; |
| #@ EMC_TRAINING_SETTLE {0x7001be44} = 0x07070404; |
| #@ EMC_TRAINING_VREF_SETTLE {0x7001be6c} = 0x00040065; |
| #@ EMC_TRAINING_CA_FINE_CTRL {0x7001be30} = 0x0513801f; |
| #@ EMC_TRAINING_CA_CTRL_MISC {0x7001be34} = 0x1f101100; |
| #@ EMC_TRAINING_CA_CTRL_MISC1 {0x7001be38} = 0x00000014; |
| #@ EMC_TRAINING_CA_VREF_CTRL {0x7001be3c} = 0x00107240; |
| #@ EMC_TRAINING_QUSE_CORS_CTRL {0x7001be0c} = 0x01124000; |
| #@ EMC_TRAINING_QUSE_FINE_CTRL {0x7001be10} = 0x01125b6a; |
| #@ EMC_TRAINING_QUSE_CTRL_MISC {0x7001be14} = 0x0f081000; |
| #@ EMC_TRAINING_QUSE_VREF_CTRL {0x7001bed0} = 0x00105800; |
| #@ EMC_TRAINING_READ_FINE_CTRL {0x7001be24} = 0x1110fc00; |
| #@ EMC_TRAINING_READ_CTRL_MISC {0x7001be28} = 0x0f081300; |
| #@ EMC_TRAINING_READ_VREF_CTRL {0x7001be2c} = 0x00105800; |
| #@ EMC_TRAINING_WRITE_FINE_CTRL {0x7001be18} = 0x1114fc00; |
| #@ EMC_TRAINING_WRITE_CTRL_MISC {0x7001be1c} = 0x07000300; |
| #@ EMC_TRAINING_WRITE_VREF_CTRL {0x7001be20} = 0x00107240; |
| #@ EMC_TRAINING_MPC {0x7001be5c} = 0x55553c5a; |
| #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000001b; |
| #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000024c; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00ff00b2; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00ff00da; |
| #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00ff009d; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00ff000c; |
| #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00ff000c; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x007f0049; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00ff0080; |
| #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x000800ad; |
| #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00ff0004; |
| #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00ff00c6; |
| #@ MC_LATENCY_ALLOWANCE_GPU2_0 {0x700193e8} = 0x00ff00c6; |
| #@ MC_LATENCY_ALLOWANCE_NVENC_0 {0x70019328} = 0x00ff006d; |
| #@ MC_LATENCY_ALLOWANCE_NVDEC_0 {0x700193d8} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00ff00e2; |
| #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000ff; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000080; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_NVJPG_0 {0x700193e4} = 0x00ff00ea; |
| #@ MC_LATENCY_ALLOWANCE_APE_0 {0x700193dc} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_TSECB_0 {0x700193f0} = 0x00ff009d; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000080; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00ff00ff; |
| #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00ff00da; |
| #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00ff0024; |
| #@ EMC_MRW10_CH0 {0x7001e4b4} = 0x880c6b6b; |
| #@ EMC_MRW10_CH1 {0x7001f4b4} = 0x880c6b6b; |
| #@ EMC_MRW11_CH0 {0x7001e4b8} = 0x480c6b6b; |
| #@ EMC_MRW11_CH1 {0x7001f4b8} = 0x480c6b6b; |
| #@ tPDEX [dvfs dram_timing] = 0x00000018; |
| #@ tRP [dvfs dram_timing] = 0x00000012; |
| #@ tRFC [dvfs dram_timing] = 0x000000b4; |
| #@ tFC_lpddr4 [dvfs dram_timing hard_coded] = 0x00000104; |
| #@ RL [dvfs dram_timing] = 0x00000006; |