Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 448d5e4..1486a1b 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -20,14 +20,16 @@
void bootblock_early_northbridge_init(void)
{
/*
- * The "io" variant of the config access is explicitly used to setup the PCIEXBAR
- * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
- * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final assumption is that
- * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+ * The "io" variant of the config access is explicitly used to setup the
+ * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way
+ * all subsequent non-explicit config accesses use MCFG. This code also
+ * assumes that bootblock_northbridge_init() is the first thing called
+ * in the non-asm boot block code. The final assumption is that no
+ * assembly code is using the CONFIG(ECAM_MMCONF_SUPPORT) option to do
+ * PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}