| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| #include <cpu/x86/msr.h> |
| #include <cpu/amd/msr.h> |
| #include <device/device.h> |
| #include <southbridge/amd/common/amd_pci_util.h> |
| |
| static const u8 mainboard_picr_data[] = { |
| 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, |
| 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, |
| }; |
| static const u8 mainboard_intr_data[84] = { |
| 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, |
| 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, |
| }; |
| |
| /* PIRQ Setup */ |
| static void pirq_setup(void) |
| { |
| intr_data_ptr = mainboard_intr_data; |
| picr_data_ptr = mainboard_picr_data; |
| } |
| |
| /* dedicated "enable" function (taken from thatcher) */ |
| static void mainboard_enable(struct device *dev) |
| { |
| msr_t msr; |
| |
| pirq_setup(); |
| |
| msr = rdmsr(LS_CFG_MSR); |
| /* Enable streaming store functionality. */ |
| msr.lo &= ~(1 << 28); |
| wrmsr(LS_CFG_MSR, msr); |
| |
| msr = rdmsr(DC_CFG_MSR); |
| /* Enable speculative TLB preloads. */ |
| msr.lo &= ~(1 << 4); |
| /* Enable the DC hardware prefetcher. */ |
| msr.lo &= ~(1 << 13); |
| wrmsr(DC_CFG_MSR, msr); |
| |
| msr = rdmsr(BU_CFG_MSR); |
| /* Disable the L2 way lock. */ |
| msr.lo &= ~(1 << 23); |
| wrmsr(BU_CFG_MSR, msr); |
| } |
| |
| struct chip_operations mainboard_ops = { |
| .enable_dev = mainboard_enable, |
| }; |