| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| #include <program_loading.h> |
| #include <console/console.h> |
| #include <cbmem.h> |
| #include <romstage_common.h> |
| |
| #include <soc/ti/am335x/sdram.h> |
| #include "ddr3.h" |
| |
| const struct ctrl_ioregs ioregs_bonelt = { |
| .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| }; |
| |
| static const struct ddr_data ddr3_beagleblack_data = { |
| .datardsratio0 = MT41K256M16HA125E_RD_DQS, |
| .datawdsratio0 = MT41K256M16HA125E_WR_DQS, |
| .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, |
| .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, |
| }; |
| |
| static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { |
| .cmd0csratio = MT41K256M16HA125E_RATIO, |
| .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| |
| .cmd1csratio = MT41K256M16HA125E_RATIO, |
| .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| |
| .cmd2csratio = MT41K256M16HA125E_RATIO, |
| .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| }; |
| |
| static struct emif_regs ddr3_beagleblack_emif_reg_data = { |
| .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, |
| .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, |
| .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, |
| .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, |
| .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, |
| .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, |
| .zq_config = MT41K256M16HA125E_ZQ_CFG, |
| .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, |
| }; |
| |
| void main(void) |
| { |
| console_init(); |
| printk(BIOS_INFO, "Hello from romstage.\n"); |
| romstage_main(); |
| } |
| |
| void __noreturn romstage_main(void) |
| { |
| config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, |
| &ddr3_beagleblack_emif_reg_data, 0); |
| |
| cbmem_initialize_empty(); |
| |
| run_ramstage(); |
| } |