| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2007-2010 coresystems GmbH |
| * Copyright (C) 2011 Google Inc |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| */ |
| |
| #include <stdint.h> |
| #include <stdlib.h> |
| #include <console/console.h> |
| #include <arch/io.h> |
| #include <device/pci_def.h> |
| #include <elog.h> |
| #include "northbridge.h" |
| |
| static void sandybridge_setup_bars(void) |
| { |
| printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| /* Set up all hardcoded northbridge BARs */ |
| pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); |
| pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); |
| pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ |
| pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); |
| pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); |
| pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32); |
| |
| /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| |
| #if CONFIG_ELOG_BOOT_COUNT |
| /* Increment Boot Counter for non-S3 resume */ |
| if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) |
| boot_count_increment(); |
| #endif |
| |
| printk(BIOS_DEBUG, " done.\n"); |
| |
| #if CONFIG_ELOG_BOOT_COUNT |
| /* Increment Boot Counter except when resuming from S3 */ |
| if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) |
| return; |
| boot_count_increment(); |
| #endif |
| } |
| |
| void sandybridge_early_initialization(int chipset_type) |
| { |
| u32 capid0_a; |
| u8 reg8; |
| |
| /* Device ID Override Enable should be done very early */ |
| capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); |
| if (capid0_a & (1 << 10)) { |
| reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); |
| reg8 &= ~7; /* Clear 2:0 */ |
| |
| if (chipset_type == SANDYBRIDGE_MOBILE) |
| reg8 |= 1; /* Set bit 0 */ |
| |
| pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); |
| } |
| |
| /* Setup all BARs required for early PCIe and raminit */ |
| sandybridge_setup_bars(); |
| } |