ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 14bbb81..06621f1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -11,6 +11,7 @@
config SOC_SPECIFIC_OPTIONS
def_bool y
+ select ACPI_HAS_DEVICE_NVS
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl
new file mode 100644
index 0000000..30bb5b5
--- /dev/null
+++ b/src/soc/intel/broadwell/acpi/device_nvs.asl
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+External (NVSD)
+
+OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
+Field (DNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Device enables in ACPI mode */
+
+ S0EN, 8, // DMA Enable
+ S1EN, 8, // I2C0 Enable
+ S2EN, 8, // I2C1 Enable
+ S3EN, 8, // SPI0 Enable
+ S4EN, 8, // SPI1 Enable
+ S5EN, 8, // UART0 Enable
+ S6EN, 8, // UART1 Enable
+ S7EN, 8, // SDIO Enable
+ S8EN, 8, // ADSP Enable
+
+ /* BAR 0 */
+
+ S0B0, 32, // DMA BAR0
+ S1B0, 32, // I2C0 BAR0
+ S2B0, 32, // I2C1 BAR0
+ S3B0, 32, // SPI0 BAR0
+ S4B0, 32, // SPI1 BAR0
+ S5B0, 32, // UART0 BAR0
+ S6B0, 32, // UART1 BAR0
+ S7B0, 32, // SDIO BAR0
+ S8B0, 32, // ADSP BAR0
+
+ /* BAR 1 */
+
+ S0B1, 32, // DMA BAR1
+ S1B1, 32, // I2C0 BAR1
+ S2B1, 32, // I2C1 BAR1
+ S3B1, 32, // SPI0 BAR1
+ S4B1, 32, // SPI1 BAR1
+ S5B1, 32, // UART0 BAR1
+ S6B1, 32, // UART1 BAR1
+ S7B1, 32, // SDIO BAR1
+ S8B1, 32, // ADSP BAR1
+}
diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl
index 880b206..fe254ff 100644
--- a/src/soc/intel/broadwell/acpi/platform.asl
+++ b/src/soc/intel/broadwell/acpi/platform.asl
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <soc/intel/broadwell/acpi/device_nvs.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/*
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h
index 2b78455..27304b5 100644
--- a/src/soc/intel/broadwell/include/soc/device_nvs.h
+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h
@@ -15,10 +15,10 @@
#define SIO_NVS_SDIO 7
#define SIO_NVS_ADSP 8
-typedef struct {
+struct __packed device_nvs {
u8 enable[9];
u32 bar0[9];
u32 bar1[9];
-} __packed device_nvs_t;
+};
#endif
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 1b6a231..70f26e8 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -4,7 +4,6 @@
#define _BROADWELL_NVS_H_
#include <stdint.h>
-#include <soc/device_nvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -35,15 +34,6 @@
u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
- u8 unused1[132]; /* 0x30 - 0xb3 - unused */
-
- u8 unused2[76];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- u8 chromeos_reserve[0xf00];
-
- /* Device specific (0x1000) */
- device_nvs_t dev;
};
#endif
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
index b83b957..88fe4b1 100644
--- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
@@ -12,7 +12,7 @@
*/
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
@@ -47,40 +47,6 @@
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
-
- Offset (0x1000),
- /* Device enables in ACPI mode */
- S0EN, 8, // DMA Enable
- S1EN, 8, // I2C0 Enable
- S2EN, 8, // I2C1 Enable
- S3EN, 8, // SPI0 Enable
- S4EN, 8, // SPI1 Enable
- S5EN, 8, // UART0 Enable
- S6EN, 8, // UART1 Enable
- S7EN, 8, // SDIO Enable
- S8EN, 8, // ADSP Enable
-
- /* BAR 0 */
- S0B0, 32, // DMA BAR0
- S1B0, 32, // I2C0 BAR0
- S2B0, 32, // I2C1 BAR0
- S3B0, 32, // SPI0 BAR0
- S4B0, 32, // SPI1 BAR0
- S5B0, 32, // UART0 BAR0
- S6B0, 32, // UART1 BAR0
- S7B0, 32, // SDIO BAR0
- S8B0, 32, // ADSP BAR0
-
- /* BAR 1 */
- S0B1, 32, // DMA BAR1
- S1B1, 32, // I2C0 BAR1
- S2B1, 32, // I2C1 BAR1
- S3B1, 32, // SPI0 BAR1
- S4B1, 32, // SPI1 BAR1
- S5B1, 32, // UART0 BAR1
- S6B1, 32, // UART1 BAR1
- S7B1, 32, // SDIO BAR1
- S8B1, 32, // ADSP BAR1
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c
index 06dd38b..a65ff4b 100644
--- a/src/soc/intel/broadwell/pch/adsp.c
+++ b/src/soc/intel/broadwell/pch/adsp.c
@@ -10,7 +10,7 @@
#include <soc/adsp.h>
#include <soc/device_nvs.h>
#include <soc/iobp.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pch.h>
#include <soc/ramstage.h>
#include <soc/rcba.h>
@@ -79,20 +79,15 @@
pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
if (config->sio_acpi_mode) {
- /* Configure for ACPI mode */
- struct global_nvs *gnvs;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
+ /* Configure for ACPI mode */
printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
-
/* Save BAR0 and BAR1 to ACPI NVS */
- gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base;
- gnvs->dev.bar1[SIO_NVS_ADSP] = (u32)bar1->base;
- gnvs->dev.enable[SIO_NVS_ADSP] = 1;
+ dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base;
+ dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base;
+ dev_nvs->enable[SIO_NVS_ADSP] = 1;
/* Set PCI Config Disable Bit */
pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD);
diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c
index d32a27d..28f34b7 100644
--- a/src/soc/intel/broadwell/pch/serialio.c
+++ b/src/soc/intel/broadwell/pch/serialio.c
@@ -8,7 +8,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/iobp.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pci_devs.h>
#include <soc/pch.h>
#include <soc/ramstage.h>
@@ -233,20 +233,15 @@
}
if (config->sio_acpi_mode) {
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0 and BAR1 to ACPI NVS */
- gnvs->dev.bar0[sio_index] = (u32)bar0->base;
- gnvs->dev.bar1[sio_index] = (u32)bar1->base;
+ dev_nvs->bar0[sio_index] = (u32)bar0->base;
+ dev_nvs->bar1[sio_index] = (u32)bar1->base;
/* Do not enable UART if it is used as debug port */
if (!serialio_uart_is_debug(dev))
- gnvs->dev.enable[sio_index] = 1;
+ dev_nvs->enable[sio_index] = 1;
/* Put device in D3hot state via BAR1 */
if (dev->path.pci.devfn != PCH_DEVFN_SDMA)