ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index afeb687..9f309b4 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -10,6 +10,7 @@
#include <soc/iosf.h>
#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -28,24 +29,19 @@
REG_SCRIPT_END
};
struct resource *bar;
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar)
- gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base;
+ dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_1);
if (bar)
- gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base;
+ dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base;
/* Device is enabled in ACPI mode */
- gnvs->dev.lpss_en[nvs_index] = 1;
+ dev_nvs->lpss_en[nvs_index] = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);